利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.029 秒)

    Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device
    2.
    发明授权
    Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device 失效
    用于减少与半导体器件中的导电通孔相关的电迁移效应的铜芯片

    公开(公告)号：US5646448A

    公开(公告)日：1997-07-08

    申请号：US699821

    申请日：1996-08-19

    申请人： Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

    发明人： Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

    CPC分类号： H01L21/76805 ,  H01L21/76877 ,  Y10S257/915 ,  Y10S438/927

    摘要： A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

    摘要翻译： 多层半导体结构包括导电通孔。 导电通孔包括具有高抗电迁移性的金属颗粒。 沉淀物由沉积在通孔上的铜或金的保形层制成，以形成位于通孔中的铜或金储存器或触点。 在储存器和绝缘层之间设置阻挡层以防止颗粒扩散到绝缘层中。 颗粒可以通过选择性沉积或通过蚀刻保形层形成。 可以通过溅射，准直溅射，化学气相沉积（CVD），浸渍，蒸发或其它方式沉积共形层。 可以通过各向异性干蚀刻，等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和颗粒。

    Uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines
    3.
    发明授权
    Uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines 失效
    用于在某些导电线之间形成低介电常数绝缘的均匀非共形沉积

    公开(公告)号：US5837618A

    公开(公告)日：1998-11-17

    申请号：US906772

    申请日：1997-08-06

    申请人： Steven Avanzino ,  Darrell Erb ,  Robin Cheung

    发明人： Steven Avanzino ,  Darrell Erb ,  Robin Cheung

    IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/56

    CPC分类号： H01L21/02164 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/31612 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

    摘要： A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposition of the nonconformal source material is stopped and a flowable insulating material, such as spin on glass, is coated on nonconformal insulating material to fill the remaining gaps. After etching the surfaces of the nonconformal and flowable insulating materials, another insulating layer is deposited and planarized to the desired overall thickness of the insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and substantially all of the remaining gaps are filled with the flowable insulating material and are void free with a composite dielectric constant of greater than about 3.5.

    摘要翻译： 在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别具有约0.5微米或更小的间隙，通过沉积绝缘材料的差的步进功能的非共形源，例如硅烷 （SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在0.5微米或更小的空隙形成之后 间隙，停止非共形源材料的沉积，并且将可流动的绝缘材料（例如玻璃上的旋涂）涂覆在非共形绝缘材料上以填充剩余的间隙。 在蚀刻非共形和可流动的绝缘材料的表面之后，另外的绝缘层被沉积并平坦化到所需绝缘体的总厚度。 或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。 所形成的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，其中间隔为0.5或更小的导电线对之间的绝缘体的介电常数与空隙结合为至少约3或 较低且基本上所有剩余的间隙都填充有可流动绝缘材料，并且无复合介电常数大于约3.5。

    Selective nonconformal deposition for forming low dielectric insulation between certain conductive lines
    4.
    发明授权
    Selective nonconformal deposition for forming low dielectric insulation between certain conductive lines 失效
    在某些导电线之间形成低介电绝缘的选择性非共形沉积

    公开(公告)号：US6048802A

    公开(公告)日：2000-04-11

    申请号：US905978

    申请日：1997-08-05

    申请人： Steven Avanzino ,  Darrell Erb ,  Robin Cheung ,  Rich Klein

    发明人： Steven Avanzino ,  Darrell Erb ,  Robin Cheung ,  Rich Klein

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/441

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

    摘要： A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After all of the conductive lines have received a deposit of conformal insulating material and a flowable insulating material, the composite insulating materials are removed, preferably by etching, from those pairs of conductive lines with a gap of about 0.5 microns or less. Now, a nonconformal insulating material with a poor step function is deposited and creates a large void in the open gaps of 0.5 microns or less. After creating the void, the deposition continues and is planarized at the desired composite thickness of insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with the gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with the flowable insulating material and are void free with a composite dielectric constant of greater than about 3.5.

    摘要翻译： 在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别具有约0.5微米或更小的间隙，通过沉积具有差的绝缘材料的步进功能的非共形源，例如硅烷 （SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在所有导电线都已经接收到保形膜 绝缘材料和可流动的绝缘材料，优选通过蚀刻从具有约0.5微米或更小的间隙的那对导电线去除复合绝缘材料。 现在，沉积具有差的阶梯函数的非共形绝缘材料，并且在0.5微米或更小的开放间隙中产生大的空隙。 在形成空隙之后，沉积继续并且在所需的绝缘复合厚度下被平坦化。 或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。 所得到的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，导电线对之间的绝缘介电常数为0.5或更小的间隙，与空隙结合为至少约3 或更低，并且所有剩余间隙都填充有可流动绝缘材料，并且无复合介电常数大于约3.5。

    Semiconductor device using uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines
    5.
    发明授权
    Semiconductor device using uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines 失效
    半导体器件使用均匀的非共形沉积法在某些导线之间形成低介电常数绝缘

    公开(公告)号：US5955786A

    公开(公告)日：1999-09-21

    申请号：US481906

    申请日：1995-06-07

    申请人： Steven Avanzino ,  Darrell Erb ,  Robin Cheung ,  Rich Klein

    发明人： Steven Avanzino ,  Darrell Erb ,  Robin Cheung ,  Rich Klein

    IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/02164 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/31612 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

    摘要： A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposition of the nonconformal source material is stopped and a flowable insulating material, such as spin on glass, is coated on nonconformal insulating material to fill the remaining gaps. After etching the surfaces of the nonconformal and flowable insulating materials, another insulating layer is deposited and planarized to the desired overall thickness of the insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and substantially all of the remaining gaps are filled with the flowable insulating material and are void free with a composite dielectric constant of greater than about 3.5.

    摘要翻译： 在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别具有约0.5微米或更小的间隙，通过沉积具有差的绝缘材料的步进功能的非共形源，例如硅烷 （SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在0.5微米或更小的空隙形成之后 间隙，停止非共形源材料的沉积，并且将可流动的绝缘材料（例如玻璃上的旋涂）涂覆在非共形绝缘材料上以填充剩余的间隙。 在蚀刻非共形和可流动的绝缘材料的表面之后，另外的绝缘层被沉积并平坦化到所需绝缘体的总厚度。 或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。 所形成的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，其中间隔为0.5或更小的导电线对之间的绝缘体的介电常数与空隙结合为至少约3或 较低且基本上所有剩余的间隙都填充有可流动绝缘材料，并且无复合介电常数大于约3.5。

    Predicting EM reliability by decoupling extrinsic and intrinsic sigma
    7.
    发明授权
    Predicting EM reliability by decoupling extrinsic and intrinsic sigma 失效
    通过去除外在和内在的sigma来预测EM的可靠性

    公开(公告)号：US07146588B1

    公开(公告)日：2006-12-05

    申请号：US10909438

    申请日：2004-08-02

    申请人： Amit P. Marathe ,  Darrell Erb

    发明人： Amit P. Marathe ,  Darrell Erb

    IPC分类号： G06F17/50 ,  G01R27/28

    CPC分类号： G01R31/2858

    摘要： Systems and methods are disclosed that facilitate predicting electromigration (EM) reliability in semiconductor wafers via decoupling intrinsic and extrinsic components of EM reliability. Electrical cross-sections of wafer test lines can be determined and individual currents can be forced through the test lines to force a constant current density across a test wafer. An EM reliability test can be performed to determine a purely intrinsic component of EM reliability. A single current can then be applied to all test lines and a second EM reliability test can be performed to determine total EM reliability. Standard deviations, or sigma, of failure distributions can be derived for each EM test. Intrinsic sigma can be subtracted from total sigma to yield an extrinsic sigma associated with process variation in wafer fabrication. Sigmas can then be utilized to predict EM reliability when process variations are adjusted, without application of a damaging package-level EM test.

    摘要翻译： 公开了通过解耦EM可靠性的内在和外在分量来促进预测半导体晶片中的电迁移（EM）可靠性的系统和方法。 可以确定晶片测试线的电气横截面，并且可以通过测试线强制单独的电流，以迫使测试晶片上的恒定电流密度。 可以进行EM可靠性测试，以确定EM可靠性的纯内在分量。 然后可以将单个电流施加到所有测试线，并且可以执行第二EM可靠性测试以确定总EM可靠性。 可以为每个EM测试导出故障分布的标准偏差或σ。 可以从总西格玛中减去本征σ，以产生与晶片制造中的工艺变化相关的外在西格玛。 然后，当调整过程变化时，可以利用Sigma来预测EM可靠性，而不应用损坏的封装级EM测试。