公开(公告)号：US20250140630A1

公开(公告)日：2025-05-01

申请号：US19009941

申请日：2025-01-04

Applicant: Richtek Technology Corporation

Inventor： Hao-Lin Yen ,  Heng-Chi Huang ,  Yong-Zhong Hu

IPC: H01L23/34 ,  H01L21/56 ,  H01L23/31

Abstract: A chip package unit includes: a base material; at least one chip, disposed on the base material; a package material, enclosing the base material and the chip; and at least one heat dissipation paste curing layer, formed by curing the heat dissipation paste, on a top side of the package material or a back side of the chip in a printed pattern.

公开(公告)号：US12272592B2

公开(公告)日：2025-04-08

申请号：US18664656

申请日：2024-05-15

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H01L21/762 ,  H10D30/65 ,  H10D62/10 ,  H10D64/27

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

公开(公告)号：US20240203840A1

公开(公告)日：2024-06-20

申请号：US18520789

申请日：2023-11-28

Applicant: Richtek Technology Corporation

Inventor： Shih-Chieh Lin ,  Min-Shun Lo ,  Heng-Chi Huang ,  Yong-Zhong Hu

IPC: H01L23/495

CPC classification number: H01L23/49544

Abstract: A lead frame includes: a die pad having a die disposing area; a plurality of lead pads located around the die pad; an outer frame, located at a periphery of the die pad and the lead pads; and at least two tie bars, respectively connected between the outer frame and two opposite sides of the die pad. At least one of the die pad and the tie bars includes a thermal deformation mitigation structure.

公开(公告)号：US12300565B2

公开(公告)日：2025-05-13

申请号：US17718125

申请日：2022-04-11

Applicant: Richtek Technology Corporation

Inventor： Hao-Lin Yen ,  Heng-Chi Huang ,  Yong-Zhong Hu

IPC: H01L23/34 ,  H01L21/56 ,  H01L23/31

Abstract: A chip package unit includes: a base material; at least one chip, disposed on the base material; a package material, enclosing the base material and the chip; and at least one heat dissipation paste curing layer, formed by curing the heat dissipation paste, on a top side of the package material or a back side of the chip in a printed pattern.

公开(公告)号：US20240105844A1

公开(公告)日：2024-03-28

申请号：US18462803

申请日：2023-09-07

Applicant: Richtek Technology Corporation

Inventor： Ying-Shiou Lin ,  Wu-Te Weng ,  Yong-Zhong Hu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L29/66492

Abstract: A native NMOS device includes: a P-type epitaxial layer, a first and a second insulation region, a first P-type well, a second P-type well, a gate, an N-type source, and an N-type drain. The P-type epitaxial layer has a first concentration of P-type doped impurities. The first P-type well completely encompasses and is in contact with a lower surface of the N-type source. The second P-type well completely encompasses and is in contact with a lower surface of the N-type drain. Each of the first P-type well and the second P-type well has a second concentration of P-type doped impurities, and the second concentration of P-type doped impurities is higher than the first concentration of P-type doped impurities. The second concentration of P-type doped impurities is sufficient for preventing a leakage current from flowing between the N-type drain and the P-type substrate while the native NMOS device is in operation.

公开(公告)号：US20220224325A1

公开(公告)日：2022-07-14

申请号：US17568637

申请日：2022-01-04

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H03K17/16

Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.

公开(公告)号：US20220181237A1

公开(公告)日：2022-06-09

申请号：US17356810

申请日：2021-06-24

Applicant: Richtek Technology Corporation

Inventor： Hao-Lin Yen ,  Heng-Chi Huang ,  Yong-Zhong Hu

IPC: H01L23/495

Abstract: The present invention provides a chip packaging method, which includes: providing a base material, which includes plural finger contacts; disposing plural chips on the base material by flip chip mounting technology, and disposing plural vertical heat conducting elements surrounding each of the chips to connect the finger contacts on the base material; providing a packaging material to encapsulate the base material, the chips, and the vertical heat conducting elements; adhering a metal film on the packaging material via an adhesive layer, to form a package structure; and cutting the package structure into plural chip package units, wherein each of the chip package units includes one of the chips, a portion of the base material, a portion of the metal film, and a portion of the vertical heat conducting elements surrounding the chip.

公开(公告)号：US20240030297A1

公开(公告)日：2024-01-25

申请号：US18314684

申请日：2023-05-09

Applicant: Richtek Technology Corporation

Inventor： Chin-Chin Tsai ,  Han-Chung Tai ,  Yong-Zhong Hu

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/41725 ,  H01L29/42376 ,  H01L29/401

Abstract: An integrated structure of semiconductor devices having a shared contact plug includes: a first device, a second device and a shared contact plug. The first device includes a first gate having a conduction region, two spacer regions and a protection region. The two spacer regions overlay and are connected with two ends of the conductive region, respectively. The protection region overlays and is connected with the spacer region located outside a shared side of the conductive region. The second device includes a shared region, wherein the shared region is located in a semiconductor layer which is located below and outside the protection region. The shared contact plug is formed on and in contact with the conductive region and the shared region. The first gate is electrically connected with the shared region through the shared contact plug, wherein the shared contact plug overlays and is connected with the protection region.

公开(公告)号：US20230238242A1

公开(公告)日：2023-07-27

申请号：US17933126

申请日：2022-09-19

Applicant: Richtek Technology Corporation

Inventor： Chin-Chin Tsai ,  Yong-Zhong Hu

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L21/28229 ,  H01L29/4916 ,  H01L21/76897 ,  H01L28/88

Abstract: A polysilicon-insulator-polysilicon (PIP) structure includes: a first polysilicon region formed on a substrate; a first insulation region formed outside one side of the first polysilicon region and adjoined to the first polysilicon region in a horizontal direction; and a second polysilicon region formed outside one side of the first insulation region. The first polysilicon region, the first insulation region and the second polysilicon region are adjoined in sequence in the horizontal direction. The second polysilicon region is formed outside the first insulation region by a first self-aligned process step, and the first insulation region is formed outside the first polysilicon region by a second self-aligned process step.

公开(公告)号：US20230163042A1

公开(公告)日：2023-05-25

申请号：US17858124

申请日：2022-07-06

Applicant: Richtek Technology Corporation

Inventor： Heng-Chi Huang ,  Sheng-Yao Wu ,  Min-Shun Lo ,  Shih-Chieh Lin ,  Yong-Zhong Hu

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/373

CPC classification number: H01L23/3675 ,  H01L25/0655 ,  H01L24/16 ,  H01L24/96 ,  H01L24/97 ,  H01L21/568 ,  H01L21/561 ,  H01L24/11 ,  H01L21/4882 ,  H01L23/3121 ,  H01L23/3735 ,  H01L2924/30101 ,  H01L2924/30107 ,  H01L2224/95001 ,  H01L24/13 ,  H01L2224/13147 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13116 ,  H01L2224/11462 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/16235 ,  H01L2924/182

Abstract: A package structure includes: a heat dissipation substrate; at least one die, including a signal transmitting side and a heat conduction side, wherein the signal transmitting side and the heat conduction side are two opposite sides on the die, and the heat conduction side is disposed on and in contact with the heat dissipation substrate; plural metal bumps, disposed on the signal transmitting side; and a package material, encapsulating the die, a side of the heat dissipation substrate in contact with the die, and the metal bumps, wherein a portion of each metal bump is exposed to an outside of the package material.