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    RECEIVERS FOR PERFORMING REFERENCE VOLTAGE TRAINING AND MEMORY SYSTEMS INCLUDING THE SAME
    1.
    发明申请
    RECEIVERS FOR PERFORMING REFERENCE VOLTAGE TRAINING AND MEMORY SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20220199126A1

    公开(公告)日：2022-06-23

    申请号：US17377654

    申请日：2021-07-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sucheol LEE ,  Changkyu SEOL ,  Byungsuk WOO

    IPC: G11C5/14 ,  G11C11/4074

    Abstract: A receiver including: a data processing circuit, in a training mode, to compare a multi-level signal with first and second voltage signals, and to generate data density signals; a counter circuit to count the data density signals to generate counting values; a control circuit to store, in a register set, a voltage range, counting values corresponding to the voltage range and a control code associated with a first level of the first voltage signal and a second level of the second voltage signal, the voltage range being based on the first and second voltage signals; and a voltage generation circuit, in the training mode, to apply the first and second voltage signals to the data processing circuit and to increase the first level and the second level by a difference between the first and second control signals in response to the control code from the control circuit.

    MEMORY DEVICE, DATA OUTPUTING METHOD THEREOF, AND MEMORY SYSTEM HAVING THE SAME
    2.
    发明申请
    MEMORY DEVICE, DATA OUTPUTING METHOD THEREOF, AND MEMORY SYSTEM HAVING THE SAME 有权

    公开(公告)号：US20220188013A1

    公开(公告)日：2022-06-16

    申请号：US17356687

    申请日：2021-06-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byungsuk WOO ,  Changkyu SEOL ,  Sucheol LEE

    IPC: G06F3/06

    Abstract: A memory device includes: a memory cell array; a data selector configured to receive data from the memory cell array, and to output the received data as first sub-data and second sub-data; a cyclic redundancy check (CRC) generator configured to generate first CRC values corresponding to the first sub-data, and to generate second CRC values corresponding to the second sub-data; a CRC selector configured to determine an order of the first CRC values and the second CRC values, and to output one of the first CRC values and one of the second CRC values according to the determined order; and a transmitter configured to receive the first CRC values and the second CRC values according to the determined order, and to transmit CRC values of the data by a multilevel signaling method.

    NEUROMORPHIC DEVICE AND NEUROMORPHIC SYSTEM INCLUDING THE SAME
    3.
    发明申请
    NEUROMORPHIC DEVICE AND NEUROMORPHIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20210160109A1

    公开(公告)日：2021-05-27

    申请号：US16911801

    申请日：2020-06-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changkyu SEOL ,  Hongrak SON ,  Geunyeong YU ,  Pilsang YOON ,  Jaehun JANG

    IPC: H04L27/04 ,  H04L27/06 ,  H04L1/00

    Abstract: A neuromorphic device includes a neuron block, a spike transmission circuit and a spike reception circuit. The neuron block includes a plurality of neurons connected by a plurality of synapses to perform generation and operation of spikes. The spike transmission circuit generates a non-binary transmission signal based on a plurality of transmission spike signals output from the neuron block and transmits the non-binary transmission signal to a transfer channel, where the non-binary transmission signal includes information on transmission spikes included in the plurality of transmission spike signals. The spike reception circuit receives a non-binary reception signal from the transfer channel and generates a plurality of reception spike signals including reception spikes based on the non-binary reception signal to provide the plurality of reception spike signals to the neuron block, where the non-binary reception signal includes information on the reception spikes.

    STORAGE DEVICE WITH ARTIFICIAL INTELLIGENCE AND STORAGE SYSTEM INCLUDING THE SAME
    7.
    发明申请
    STORAGE DEVICE WITH ARTIFICIAL INTELLIGENCE AND STORAGE SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20210150321A1

    公开(公告)日：2021-05-20

    申请号：US16906209

    申请日：2020-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehun JANG ,  Hongrak SON ,  Changkyu SEOL ,  Hyejeong SO ,  Hwaseok OH ,  Pilsang YOON ,  Jinsoo LIM

    IPC: G06N3/063 ,  G06N3/08 ,  G06F7/544 ,  G06F15/80

    Abstract: A storage system includes a host device and a storage device. The host device provides first input data for data storage function and second input data for artificial intelligence (AI) function. The storage device stores the first input data from the host device, and performs AI calculation based on the second input data to generate calculation result data. The storage device includes a first processor, a first nonvolatile memory, a second processor and a second nonvolatile memory. The first processor controls an operation of the storage device. The first nonvolatile memory stores the first input data. The second processor performs the AI calculation, and is distinguished from the first processor. The second nonvolatile memory stores weight data associated with the AI calculation, and is distinguished from the first nonvolatile memory.

    TRANSMITTER AND RECEIVER FOR 3-LEVEL PULSE AMPLITUDE MODULATION SIGNALING AND SYSTEM INCLUDING THE SAME
    8.
    发明公开
    TRANSMITTER AND RECEIVER FOR 3-LEVEL PULSE AMPLITUDE MODULATION SIGNALING AND SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230344444A1

    公开(公告)日：2023-10-26

    申请号：US17975034

    申请日：2022-10-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changkyu SEOL ,  Sungrae KIM ,  Chisung OH ,  Junghwan CHOI

    IPC: H03M5/14 ,  H04L1/00

    CPC classification number: H03M5/145 ,  H04L1/0009 ,  H04L1/0014

    Abstract: A transmitter includes an encoder configured to divide a first number of binary input bits of an input data signal into a first bit group and a second bit group, generate a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group differently based on a value of the first bit group, and generate a first symbol group and a second symbol group by encoding the first intermediate bit group and the second intermediate bit group, each of the first symbol group and the second symbol group including a plurality of symbols, and each of the plurality of symbols having three different voltage levels. The transmitter includes a driver configured to generate an output data signal by concatenating the first symbol group and the second symbol group.

    METHODS OF CONTROLLING OPERATION OF NONVOLATILE MEMORY DEVICES AND DATA CONVERTERS FOR PERFORMING THE SAME
    9.
    发明申请
    METHODS OF CONTROLLING OPERATION OF NONVOLATILE MEMORY DEVICES AND DATA CONVERTERS FOR PERFORMING THE SAME 有权

    公开(公告)号：US20210157672A1

    公开(公告)日：2021-05-27

    申请号：US16891517

    申请日：2020-06-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changkyu SEOL ,  Hyejeong SO ,  Kwanwoo NOH ,  Hongrak SON ,  Pilsang YOON

    IPC: G06F11/10 ,  H03M13/13

    Abstract: Channel selection information indicate positions of data bits of input data, positions of error correction code (ECC) parity bits for correcting errors in the input data, and positions of state shaping parity bits. The ECC parity bits and the state shaping parity bits are generated to cause a decrease in a quantity of memory cells, of the plurality of memory cells, in which at least one target state among a plurality of states is programmed. An alignment vector is generated based on aligning the data bits of the input data, the ECC parity bits, and the state shaping parity bits, based on the channel selection information. A codeword is generated based on simultaneously performing state shaping and ECC encoding with respect to the alignment vector. Write data are written in the nonvolatile memory device based on the codeword.

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