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    METHODS OF CONTROLLING OPERATION OF NONVOLATILE MEMORY DEVICES AND DATA CONVERTERS FOR PERFORMING THE SAME
    1.
    发明申请
    METHODS OF CONTROLLING OPERATION OF NONVOLATILE MEMORY DEVICES AND DATA CONVERTERS FOR PERFORMING THE SAME 有权

    公开(公告)号：US20210157672A1

    公开(公告)日：2021-05-27

    申请号：US16891517

    申请日：2020-06-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changkyu SEOL ,  Hyejeong SO ,  Kwanwoo NOH ,  Hongrak SON ,  Pilsang YOON

    IPC: G06F11/10 ,  H03M13/13

    Abstract: Channel selection information indicate positions of data bits of input data, positions of error correction code (ECC) parity bits for correcting errors in the input data, and positions of state shaping parity bits. The ECC parity bits and the state shaping parity bits are generated to cause a decrease in a quantity of memory cells, of the plurality of memory cells, in which at least one target state among a plurality of states is programmed. An alignment vector is generated based on aligning the data bits of the input data, the ECC parity bits, and the state shaping parity bits, based on the channel selection information. A codeword is generated based on simultaneously performing state shaping and ECC encoding with respect to the alignment vector. Write data are written in the nonvolatile memory device based on the codeword.

    NEUROMORPHIC DEVICE AND NEUROMORPHIC SYSTEM INCLUDING THE SAME
    2.
    发明申请
    NEUROMORPHIC DEVICE AND NEUROMORPHIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20210160109A1

    公开(公告)日：2021-05-27

    申请号：US16911801

    申请日：2020-06-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changkyu SEOL ,  Hongrak SON ,  Geunyeong YU ,  Pilsang YOON ,  Jaehun JANG

    IPC: H04L27/04 ,  H04L27/06 ,  H04L1/00

    Abstract: A neuromorphic device includes a neuron block, a spike transmission circuit and a spike reception circuit. The neuron block includes a plurality of neurons connected by a plurality of synapses to perform generation and operation of spikes. The spike transmission circuit generates a non-binary transmission signal based on a plurality of transmission spike signals output from the neuron block and transmits the non-binary transmission signal to a transfer channel, where the non-binary transmission signal includes information on transmission spikes included in the plurality of transmission spike signals. The spike reception circuit receives a non-binary reception signal from the transfer channel and generates a plurality of reception spike signals including reception spikes based on the non-binary reception signal to provide the plurality of reception spike signals to the neuron block, where the non-binary reception signal includes information on the reception spikes.

    STORAGE DEVICE WITH ARTIFICIAL INTELLIGENCE AND STORAGE SYSTEM INCLUDING THE SAME
    6.
    发明申请
    STORAGE DEVICE WITH ARTIFICIAL INTELLIGENCE AND STORAGE SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20210150321A1

    公开(公告)日：2021-05-20

    申请号：US16906209

    申请日：2020-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehun JANG ,  Hongrak SON ,  Changkyu SEOL ,  Hyejeong SO ,  Hwaseok OH ,  Pilsang YOON ,  Jinsoo LIM

    IPC: G06N3/063 ,  G06N3/08 ,  G06F7/544 ,  G06F15/80

    Abstract: A storage system includes a host device and a storage device. The host device provides first input data for data storage function and second input data for artificial intelligence (AI) function. The storage device stores the first input data from the host device, and performs AI calculation based on the second input data to generate calculation result data. The storage device includes a first processor, a first nonvolatile memory, a second processor and a second nonvolatile memory. The first processor controls an operation of the storage device. The first nonvolatile memory stores the first input data. The second processor performs the AI calculation, and is distinguished from the first processor. The second nonvolatile memory stores weight data associated with the AI calculation, and is distinguished from the first nonvolatile memory.

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