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公开(公告)号:US20250125321A1
公开(公告)日:2025-04-17
申请号:US18775260
申请日:2024-07-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junghoon Kang , Daegon Kim
IPC: H01L25/16 , G02B6/42 , G02B6/43 , H01L23/00 , H01L23/13 , H01L23/31 , H01L23/48 , H01L23/49 , H01L23/538 , H01L27/144
Abstract: An example semiconductor package includes a package substrate, an electronic integrated circuit (EIC) package mounted on the package substrate, and a plurality of photonic integrated circuit (PIC) chips stacked on the EIC package. Each PIC chip of the plurality of PIC chips includes an upper groove recessed inwards from an upper surface of the PIC chip and being open toward a first side surface of the PIC chip. The EIC package includes a lower redistribution layer on the package substrate, an EIC chip mounted on the lower redistribution layer, a molding layer surrounding the EIC chip, a through via passing through the molding layer in a vertical direction and electrically connected with the lower redistribution layer, and an upper redistribution layer on the through via.
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公开(公告)号:US20250123447A1
公开(公告)日:2025-04-17
申请号:US18787653
申请日:2024-07-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junghoon Kang , Daegon Kim
IPC: G02B6/42
Abstract: Provided is a semiconductor package including a package substrate and a photonic integrated circuit chip arranged on the package substrate, having a groove extending from a lateral surface of the photonic integrated circuit chip to the inside of the photonic integrated circuit chip, and including a photoelectric converter, wherein the photoelectric converter includes a light-emitting device configured to generate an optical signal, a first waveguide connected to the light-emitting device and providing a path through which the optical signal travels, a first grating coupler configured to output the optical signal, a second waveguide connected to first grating coupler, and a tunable coupler connected to the first waveguide and the second waveguide.
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3.
公开(公告)号:US11798814B2
公开(公告)日:2023-10-24
申请号:US17827966
申请日:2022-05-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junghoon Kang
IPC: H01L21/48 , H01L23/538 , H01L25/18 , H01L25/00 , H01L21/683 , H01L23/498
CPC classification number: H01L21/4857 , H01L21/4853 , H01L21/6835 , H01L23/5383 , H01L25/18 , H01L25/50 , H01L23/49811 , H01L2221/68381
Abstract: A semiconductor package includes an interposer having a separation layer on a rear surface of which a plurality of first recesses is arranged. A plurality of wiring structures is stacked on the separation layer alternately with a plurality of insulation interlayers. A plurality of semiconductor devices is arranged, side by side, on the interposer side and connected to a plurality of the wiring structures. A plurality of contact terminals on the rear surface of the separation layer is connected to the plurality of the wiring structures through the separation layer. A flatness deterioration of the interposer is minimized and the contact surface between the interposer and under fill resin is enlarged.
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公开(公告)号:US20250125312A1
公开(公告)日:2025-04-17
申请号:US18773021
申请日:2024-07-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junghoon Kang , Daegon Kim
IPC: H01L25/065 , G02B6/42 , G02B6/43 , H01L23/00 , H01L23/13 , H01L23/48 , H01L23/498 , H01L23/538 , H01L27/144
Abstract: A semiconductor package includes a package substrate, an electronic integrated circuit chip mounted on the package substrate, a first photonic integrated circuit chip mounted on the electronic integrated circuit chip, the first photonic integrated circuit chip including a first groove recessed from a top surface and a side surface of the first photonic integrated circuit chip, and a second photonic integrated circuit chip mounted on the first photonic integrated circuit chip, the second photonic integrated circuit chip including a second groove recessed from a top surface and a side surface of the second photonic integrated circuit chip, wherein the second photonic integrated circuit chip is offset-stacked on the first photonic integrated circuit chip, wherein at least a portion of a bottom surface of the first groove of the first photonic integrated circuit chip is exposed to the outside.
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公开(公告)号:US20250087651A1
公开(公告)日:2025-03-13
申请号:US18646858
申请日:2024-04-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Junghoon Kang , Daegon Kim
IPC: H01L25/16 , H01L23/00 , H01L23/04 , H01L23/48 , H01L23/498
Abstract: A semiconductor package includes a package substrate including a first surface and a second surface opposite the first surface, a die disposed on the first surface of the package substrate, a stack structure disposed on the first surface of the package substrate and spaced apart from the die in a horizontal direction, and a socket disposed between the first surface of the package substrate and the stack structure and coupling the package substrate and the stack structure to each other, wherein the stack structure includes a plurality of optical integrated circuit chips stacked vertically with each other.
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公开(公告)号:US20250022859A1
公开(公告)日:2025-01-16
申请号:US18427622
申请日:2024-01-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junghoon Kang
IPC: H01L25/16 , H01L21/48 , H01L23/00 , H01L23/13 , H01L23/31 , H01L23/498 , H01L23/538 , H01L23/58 , H01L21/56
Abstract: A semiconductor package includes a wiring substrate and a first semiconductor chip disposed on the wiring substrate. The wiring substrate includes a first core portion including glass and having a cavity that vertically penetrates the first core portion, first core vias that each vertically penetrate the first core portion, a passive device in the cavity of the first core portion, a buried material on the first core portion and the first core vias and filling the cavity and covering a top surface and outer lateral surfaces of the first core portion, and an upper buildup portion disposed on the buried material. The upper buildup portion includes a first dielectric pattern, and a first wiring pattern that penetrates the first dielectric pattern and the buried material and is coupled to the first core vias.
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7.
公开(公告)号:US20220293432A1
公开(公告)日:2022-09-15
申请号:US17827966
申请日:2022-05-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junghoon Kang
IPC: H01L21/48 , H01L23/538 , H01L25/18 , H01L25/00 , H01L21/683
Abstract: A semiconductor package includes an interposer having a separation layer on a rear surface of which a plurality of first recesses is arranged. A plurality of wiring structures is stacked on the separation layer alternately with a plurality of insulation interlayers. A plurality of semiconductor devices is arranged, side by side, on the interposer side and connected to a plurality of the wiring structures. A plurality of contact terminals on the rear surface of the separation layer is connected to the plurality of the wiring structures through the separation layer. A flatness deterioration of the interposer is minimized and the contact surface between the interposer and under fill resin is enlarged.
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公开(公告)号:US20250093594A1
公开(公告)日:2025-03-20
申请号:US18747906
申请日:2024-06-19
Applicant: Samsung Electronics Co., Ltd.
Inventor: Junghoon Kang , Daegon Kim
IPC: G02B6/42 , H01L23/00 , H01L23/13 , H01L23/48 , H01L23/498 , H01L23/538 , H01L25/16 , H01L27/144
Abstract: A semiconductor package includes a package substrate including an alignment hole extending inwardly from a side surface of the package substrate, a photonic integrated circuit chip disposed on the package substrate, the of the package substrate chip including a groove extending inwardly from a side surface of the PIC chip and a photo-electron conversion unit including an edge coupler, and an optical fiber connector including a frame, an optical fiber mounted in the groove of the of the package substrate chip and passing through the frame, and an alignment pin extending from the frame to an inside of the alignment hole, wherein the edge coupler is located at one end of the photo-electron conversion unit.
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公开(公告)号:US12100668B2
公开(公告)日:2024-09-24
申请号:US18496372
申请日:2023-10-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junghoon Kang
IPC: H01L23/31 , H01L23/00 , H01L23/538 , H01L23/544 , H01L25/065
CPC classification number: H01L23/544 , H01L23/3121 , H01L23/5384 , H01L23/5386 , H01L24/16 , H01L25/0657 , H01L2224/16225 , H01L2225/06517
Abstract: A semiconductor package includes a first semiconductor chip; an encapsulant covering at least a portion of the first semiconductor chip; insulating layers provided on the encapsulant, each of the insulating layers being transparent or translucent; and wiring layers provided on the encapsulant, the wiring layers being partially covered by the insulating layers, wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, a color of the first region is different from a color of the second region, the second region surrounds the first region, and at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer.
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公开(公告)号:US20240213174A1
公开(公告)日:2024-06-27
申请号:US18515797
申请日:2023-11-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Junghoon Kang , Unbyoung Kang , Jinsu Kim , Seungwan Shin , Byoungwook Jang
IPC: H01L23/544 , H01L23/00 , H01L23/31 , H01L23/498 , H01L25/065 , H01L25/10
CPC classification number: H01L23/544 , H01L23/3128 , H01L23/49811 , H01L24/16 , H01L24/20 , H01L25/0657 , H01L25/105 , H01L2223/54433 , H01L2224/16225 , H01L2224/21 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562
Abstract: A semiconductor package includes a lower redistribution wiring layer having a first region and a second region adjacent the first region and including first redistribution wirings; a semiconductor chip on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a sealing member on a side surface of the semiconductor chip and on the lower redistribution wiring layer; a plurality of vertical conductive structures penetrating the sealing member on the second region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a marking pattern on the semiconductor chip; seed layer pads on respective end portions of the vertical conductive structures that are exposed by the sealing member at an upper surface thereof; and an upper redistribution wiring layer on the sealing member and the marking pattern and including second redistribution wirings.
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