公开(公告)号：US20250105183A1

公开(公告)日：2025-03-27

申请号：US18817305

申请日：2024-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung Chul SHIN ,  Won IL LEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/18

Abstract: According to example embodiments of the present inventive concept, a semiconductor chip includes: a semiconductor substrate including a first surface and a second surface that is opposite to the first surface; a through-via disposed in the semiconductor substrate; a first bonding pad disposed on the first surface of the semiconductor substrate and electrically connected to the through-via; a first dummy pad disposed on the first surface of the semiconductor substrate and insulated from the through-via; and a second bonding pad disposed on the second surface of the semiconductor substrate and electrically connected to the through-via, wherein a first maximum width of the first bonding pad is greater than a second maximum width in a first direction of the first dummy pad and is smaller than a third maximum width in a second direction of the first dummy pad, and wherein the first direction is substantially perpendicular to the second direction.

公开(公告)号：US20240258278A1

公开(公告)日：2024-08-01

申请号：US18500089

申请日：2023-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungchul SHIN ,  Won IL LEE ,  Hyuekjae LEE ,  Enbin JO

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L25/18 ,  H10B80/00 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13117 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/01058 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433

Abstract: A semiconductor package includes a lower semiconductor chip, a first semiconductor chip, a first through-electrode vertically penetrating the first semiconductor substrate, a first upper pad connected to the first through electrode, a first circuit layer disposed on the lower surface of the first semiconductor substrate, and a first lower pad disposed on a lower surface of the first circuit layer. A second semiconductor chip includes a second through-electrode spaced apart from the first through-electrode and vertically penetrating the second semiconductor substrate. A second upper pad is connected to the second through electrode. A second circuit layer is disposed on the lower surface of the second semiconductor substrate, and a second lower pad is connected to the second through-electrode on the lower surface of the second circuit layer through the second circuit layer and is integrally formed with the first upper pad.