公开(公告)号：US20240162184A1

公开(公告)日：2024-05-16

申请号：US18337113

申请日：2023-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Sick Park ,  Un-Byoung Kang ,  Min Soo Kim ,  Seon Gyo Kim

IPC: H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L24/33 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/3003 ,  H01L2224/30505 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83856 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2924/0665 ,  H01L2924/067 ,  H01L2924/07025 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443

Abstract: A semiconductor package includes a first structure, a first semiconductor chip on the first structure, a first conductive pad on the first structure between the first structure and the first semiconductor chip, a second conductive pad on a lower surface of the first semiconductor chip and vertically overlapping the first conductive pad, a bump connecting the first conductive pad and the second conductive pad, a first adhesive layer surrounding at least a part of side walls of the bump and side walls of the first conductive pad, and a second adhesive layer surrounding at least a part of the side walls of the bump and side walls of the second conductive pad, the second adhesive layer including a material different from the first adhesive layer, wherein a horizontal width of the first adhesive layer is smaller than a horizontal width of the second adhesive layer.

公开(公告)号：US20180132394A1

公开(公告)日：2018-05-10

申请号：US15670007

申请日：2017-08-07

Applicant: SET North America, LLC

Inventor： Eric Frank Schulte

IPC: H05K13/04 ,  H01L25/00 ,  H01L23/00

CPC classification number: H05K13/046 ,  B32B38/0008 ,  B32B2310/14 ,  B32B2457/00 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/1181 ,  H01L2224/11831 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/81011 ,  H01L2224/81013 ,  H01L2224/81054 ,  H01L2224/81099 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81201 ,  H01L2224/81365 ,  H01L2224/81895 ,  H01L2224/81897 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2924/00 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1461

Abstract: Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.

公开(公告)号：US20170243856A1

公开(公告)日：2017-08-24

申请号：US15393754

申请日：2016-12-29

Applicant: Sang-Sick PARK ,  Geol NAM ,  Tae Hong MIN ,  Jihwan HWANG

Inventor： Sang-Sick PARK ,  Geol NAM ,  Tae Hong MIN ,  Jihwan HWANG

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13117 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16113 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/9211 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/01058 ,  H01L2924/0665 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2224/83 ,  H01L2224/81

Abstract: A semiconductor package includes a plurality of semiconductor chips on a substrate. The semiconductor chips include a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip that are sequentially stacked on the substrate. The semiconductor package further includes a plurality of non-conductive layers between the substrate and the first semiconductor chip and between adjacent semiconductor chips among the semiconductor chips. The semiconductor chips include smaller widths as a distance from the substrate increases. Each of the non-conductive layers includes an extension protruding outward from a side surface of an overlying one of the semiconductor chips.

公开(公告)号：US09269887B1

公开(公告)日：2016-02-23

申请号：US14619927

申请日：2015-02-11

Applicant: TriQuint Semiconductor, Inc.

Inventor： Frank J. Juskey ,  Robert C. Hartmann ,  Thomas S. Morris ,  Howard T. Glascock ,  Jose F. Ordonez

IPC: H01L23/31 ,  H01L41/311 ,  H01L41/053 ,  H01L41/08 ,  H01L41/25 ,  H01L25/16 ,  H01L23/36 ,  H01L23/538

CPC classification number: H01L23/5383 ,  H01L23/36 ,  H01L23/5384 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/065 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2924/1531 ,  H01L2924/15313 ,  H01L2924/1532 ,  H01L2924/15323 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/3025

Abstract: Embodiments include but are not limited to apparatuses and systems including microelectronic devices including a package substrate, a plurality of electronic components disposed on and electrically coupled with the package substrate at one or more sides of the package substrate, one or more hollow cavity sheet molds surrounding the plurality of electronic components and coupled with one or more sides of the package substrate, and a plurality of through-mold vias to couple the package substrate with an external surface of at least one of the one or more hollow cavity sheet molds. The microelectronic device may be a chip-scale package or module. Methods and systems for making the same also are described.

Abstract translation: 实施例包括但不限于包括微电子器件的设备和系统，包括封装衬底，在封装衬底的一个或多个侧面上设置并与封装衬底电耦合的多个电子元件，一个或多个空腔模片周围 所述多个电子部件并且与所述封装基板的一个或多个侧面耦合，以及多个通孔模具通孔，以将所述封装基板与所述一个或多个中空型腔模具中的至少一个的外表面耦合。 微电子器件可以是芯片级封装或模块。 还描述了制造它们的方法和系统。

公开(公告)号：US20150270241A1

公开(公告)日：2015-09-24

申请号：US14667490

申请日：2015-03-24

Applicant: Efficient Power Conversion Corporation

Inventor： ROBERT STRITTMATTER ,  Seshadri Kolluri ,  Robert Beach ,  Jianjun Cao ,  Alana Nakata

IPC: H01L23/00 ,  B23K1/00

CPC classification number: H01L24/81 ,  B23K1/0004 ,  B23K1/0016 ,  B23K3/047 ,  B23K3/0623 ,  B23K2101/42 ,  H01L23/4824 ,  H01L23/49844 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/16227 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/2912 ,  H01L2224/32227 ,  H01L2224/8112 ,  H01L2224/81234 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/8312 ,  H01L2224/83234 ,  H01L2224/83447 ,  H01L2224/83815 ,  H01L2924/1306 ,  H01L2924/1461 ,  H05K1/0265 ,  H05K2201/09672 ,  H05K2201/10166 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device.

Abstract translation: 一种用于将半导体器件与倒装芯片形状电连接到印刷电路板的方法和系统。 该方法的示例性实施例包括：将器件上的焊接触点与外部电路的第一铜触点和第二铜触点对准，并且仅将电源电流直接施加到第一铜的掩埋层，而不是直接连接到 层，其最接近设备，使得没有电流通过最靠近设备的层来源到设备。

公开(公告)号：US09053989B2

公开(公告)日：2015-06-09

申请号：US13228094

申请日：2011-09-08

Applicant: Chen-Cheng Kuo ,  Chita Chuang ,  Tsung-Shu Lin ,  Chen-Shien Chen

Inventor： Chen-Cheng Kuo ,  Chita Chuang ,  Tsung-Shu Lin ,  Chen-Shien Chen

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05026 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/141 ,  H01L2224/14135 ,  H01L2224/16059 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01013 ,  H01L2924/01073 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01024 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/0104 ,  H01L2924/206 ,  H01L2924/01082 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/13012 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A device includes a chip attached to a substrate. The chip includes a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a conductive trace and a mask layer overlying the conductive trace, wherein the mask layer has an opening exposing a portion of the conductive trace. An interconnection is formed between the conductive pillar and the exposed portion of the conductive trace. The opening has a first dimension (d1) measured along the long axis of the conductive pillar and a second dimension (d2) measured along the short axis of the conductive pillar. A ratio of L to d1 is greater than a ratio of W to d2.

Abstract translation: 一种器件包括附接到衬底的芯片。 该芯片包括具有沿着导电柱的长轴测量的长度（L）和沿导电柱的短轴测量的宽度（W）的导电柱。 衬底包括覆盖导电迹线的导电迹线和掩模层，其中掩模层具有暴露导电迹线的一部分的开口。 在导电柱和导电迹线的暴露部分之间形成互连。 开口具有沿着导电柱的长轴测量的第一尺寸（d1）和沿着导电柱的短轴测量的第二尺寸（d2）。 L与d1的比值大于W与d2的比。

公开(公告)号：US20140374912A1

公开(公告)日：2014-12-25

申请号：US13925753

申请日：2013-06-24

Applicant: Palo Alto Research Center Incorporated

Inventor： John C. Knights

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/06051 ,  H01L2224/06154 ,  H01L2224/06515 ,  H01L2224/1111 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13027 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/1318 ,  H01L2224/13184 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14154 ,  H01L2224/14505 ,  H01L2224/16105 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17517 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81902 ,  H01L2224/81905 ,  H01L2924/12041 ,  H05K3/32 ,  H05K3/341 ,  H05K2201/0311 ,  H05K2201/10674 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2924/01074 ,  H01L2924/0104 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: Standard solder-based interconnect structures are utilized as mechanical fasteners to attach an IC die in a “flip-chip” orientation to a support structure (e.g., a package base substrate or printed circuit board). Electrical connections between the support structure and the IC die are achieved by curved micro-springs that are disposed in peripheral regions of the IC die and extend through a gap region separating the upper structure surface and the processed surface of the IC die. The micro-springs are fixedly attached to one of the support structure and the IC die, and have a free (tip) end that contacts an associated contact pad disposed on the other structure/IC die. Conventional solder-based connection structures (e.g., solder-bumps/balls) are disposed on “dummy” (non-functional) pads disposed in a central region of the IC die. After placing the IC die on the support structure, a standard solder reflow process is performed to complete the mechanical connection.

Abstract translation: 标准的基于焊料的互连结构被用作机械紧固件，以将“芯片”取向的IC管芯连接到支撑结构（例如，封装基底或印刷电路板）上。 支撑结构和IC芯片之间的电连接通过设置在IC管芯的周边区域中的弯曲的微型弹簧实现，并且延伸穿过分离IC模具的上部结构表面和加工表面的间隙区域。 微弹簧固定地附接到支撑结构和IC模具中的一个，并且具有与设置在另一个结构/ IC芯片上的相关接触焊盘接触的自由（尖端）端。 常规的基于焊料的连接结构（例如，焊料凸起/球）设置在设置在IC管芯的中心区域中的“虚拟”（非功能）焊盘上。 将IC管芯放置在支撑结构上之后，进行标准的回流焊工艺以完成机械连接。

公开(公告)号：US20140332953A1

公开(公告)日：2014-11-13

申请号：US13892367

申请日：2013-05-13

Applicant: Infineon Technologies AG

Inventor： Peter Ossimitz ,  Robert Bauer ,  Tobias Jacobs

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/11903 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1411 ,  H01L2224/17107 ,  H01L2224/81193 ,  H01L2924/0002 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/207 ,  H01L2924/01047

Abstract: A chip arrangement may include: a chip including a plurality of electrical nets, wherein each electrical net includes at least one bonding pad; and a plurality of pillars formed on the at least one bonding pad of a majority of the plurality of electrical nets, wherein the plurality of pillars may be configured to connect the at least one bonding pad of the majority of the plurality of electrical nets to a chip-external connection region.

Abstract translation: 芯片布置可以包括：包括多个电网的芯片，其中每个电网包括至少一个焊盘; 以及形成在所述多个电网中的大多数的所述至少一个焊盘上的多个柱，其中所述多个柱可以被配置为将所述多个电网中的大多数的所述至少一个焊盘连接到 芯片外部连接区域。

公开(公告)号：US08614512B2

公开(公告)日：2013-12-24

申请号：US13615804

申请日：2012-09-14

Applicant: Luc Guerin ,  Mario J. Interrante ,  Michael J. Shapiro ,  Thuy Tran-Quinn ,  Van T. Truong

Inventor： Luc Guerin ,  Mario J. Interrante ,  Michael J. Shapiro ,  Thuy Tran-Quinn ,  Van T. Truong

IPC: H01L29/40

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05681 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2224/05552

Abstract: A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

公开(公告)号：US20130334656A1

公开(公告)日：2013-12-19

申请号：US13797655

申请日：2013-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggi JIN ,  Jeong-woo PARK ,  Ju-il Choi

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L23/293 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/10126 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Provided are electrical connection structures and methods of fabricating the same. The structures may include a substrate including a bonding pad region provided with a bonding pad and a fuse region provided with a fuse, an insulating layer provided on the substrate and including a bonding pad opening exposing the bonding pad and a fuse opening exposing the fuse region, a connection terminal provided in the bonding pad region and electrically connected to the bonding pad, and a protection layer provided on the insulating layer including a first protection layer provided within the bonding pad region and a second protection layer in the fuse opening.

Abstract translation: 提供电连接结构及其制造方法。 该结构可以包括：衬底，其包括具有接合焊盘的接合焊盘区域和设置有保险丝的熔断器区域，设置在衬底上的绝缘层，并且包括露出焊盘的焊盘开口和暴露熔丝区域的保险丝开口 设置在所述焊盘区域中并且电连接到所述焊盘的连接端子，以及设置在所述绝缘层上的保护层，所述保护层包括设置在所述焊盘区域内的第一保护层和所述熔丝开口中的第二保护层。