公开(公告)号：US10014267B2

公开(公告)日：2018-07-03

申请号：US15145231

申请日：2016-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Sang Cho ,  Sang-Woo Pae ,  Hyun-Suk Chun ,  Young-Seok Jung

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/31 ,  H01L23/525

CPC classification number: H01L24/02 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/585 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02235 ,  H01L2224/0235 ,  H01L2224/0237 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/141 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/0231 ,  H01L2224/11

Abstract: A semiconductor device comprises a semiconductor chip which includes at least one gate structure on a substrate, the gate structure including a first region, a second region different from the first region, and a third region between the first and the second region, a first redistribution layer on a top surface of the semiconductor chip, the first redistribution layer configured to electrically connect a first electrode pad of the semiconductor chip to a first solder ball and overlap the first region of the gate structure, a second redistribution layer on the top surface of the semiconductor chip, the second redistribution layer configured to electrically connect a second electrode pad of the semiconductor chip to a second solder ball and overlap the second region of the gate structure such that the third region is exposed, and an insulating layer on the first redistribution layer and the second redistribution layer.

公开(公告)号：US20140217490A1

公开(公告)日：2014-08-07

申请号：US13803791

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bo-Young Seo ,  Weon-Ho Park ,  Chang-Min Jeon ,  Yong-Sang Cho

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

Abstract: In a nonvolatile memory device and a method for fabricating the same, a device comprises a substrate, a trench in the substrate and a first gate pattern comprising a first bottom gate electrode having a first portion in the trench and having a second portion on the first portion and protruding in an upward direction relative to an upper surface of the substrate. A second gate pattern comprising a second gate electrode is on the substrate at a side of the first gate pattern and insulated from the first gate pattern. An impurity region is present in the substrate at a side of the first gate pattern opposite the second gate pattern, and overlapping part of the trench.

Abstract translation: 在非易失性存储器件及其制造方法中，器件包括衬底，衬底中的沟槽和第一栅极图案，第一栅极图案包括第一底部栅极电极，第一底部栅电极在沟槽中具有第一部分，并且在第一 并相对于基板的上表面向上方突出。 包括第二栅电极的第二栅极图案在第一栅极图案的一侧的基板上，并与第一栅极图案绝缘。 在第一栅极图案的与第二栅极图案相对的一侧上存在杂质区域和沟槽的重叠部分。

公开(公告)号：US20160049320A1

公开(公告)日：2016-02-18

申请号：US14635147

申请日：2015-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeon-sik Choo ,  Soo-Jae Park ,  Jae-Heon Noh ,  Yong-Sang Cho

IPC: H01L21/673

CPC classification number: H01L21/67393

Abstract: A wafer carrier comprises a body part constructed and arranged to accommodate a wafer and including first and second layers which are stacked in sequence. A cover is mountable to the body part. A first air filter is positioned on the cover. A second air filter is positioned on a side of the body part. The second layer is positioned between the first layer and an inner region of the body part. A surface of the second layer facing the inner region is subjected to charge prevention processing.

Abstract translation: 晶片载体包括被构造和布置成容纳晶片并包括按顺序堆叠的第一和第二层的主体部分。 一个盖可以安装到身体部位。 第一个空气过滤器位于盖子上。 第二空气过滤器位于身体部分的一侧。 第二层位于主体部分的第一层和内部区域之间。 面对内部区域的第二层的表面经受电荷防止处理。

公开(公告)号：US09396979B2

公开(公告)日：2016-07-19

申请号：US14635147

申请日：2015-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeon-sik Choo ,  Soo-Jae Park ,  Jae-Heon Noh ,  Yong-Sang Cho

IPC: H01L21/673

CPC classification number: H01L21/67393

Abstract: A wafer carrier comprises a body part constructed and arranged to accommodate a wafer and including first and second layers which are stacked in sequence. A cover is mountable to the body part. A first air filter is positioned on the cover. A second air filter is positioned on a side of the body part. The second layer is positioned between the first layer and an inner region of the body part. A surface of the second layer facing the inner region is subjected to charge prevention processing.

Abstract translation: 晶片载体包括构造和布置成容纳晶片并包括依次层叠的第一和第二层的主体部分。 一个盖可以安装到身体部位。 第一个空气过滤器位于盖子上。 第二空气过滤器位于身体部分的一侧。 第二层位于主体部分的第一层和内部区域之间。 面对内部区域的第二层的表面经受电荷防止处理。