公开(公告)号：US10014267B2

公开(公告)日：2018-07-03

申请号：US15145231

申请日：2016-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Sang Cho ,  Sang-Woo Pae ,  Hyun-Suk Chun ,  Young-Seok Jung

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/31 ,  H01L23/525

CPC classification number: H01L24/02 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/585 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02235 ,  H01L2224/0235 ,  H01L2224/0237 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/141 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/0231 ,  H01L2224/11

Abstract: A semiconductor device comprises a semiconductor chip which includes at least one gate structure on a substrate, the gate structure including a first region, a second region different from the first region, and a third region between the first and the second region, a first redistribution layer on a top surface of the semiconductor chip, the first redistribution layer configured to electrically connect a first electrode pad of the semiconductor chip to a first solder ball and overlap the first region of the gate structure, a second redistribution layer on the top surface of the semiconductor chip, the second redistribution layer configured to electrically connect a second electrode pad of the semiconductor chip to a second solder ball and overlap the second region of the gate structure such that the third region is exposed, and an insulating layer on the first redistribution layer and the second redistribution layer.

公开(公告)号：US09368465B2

公开(公告)日：2016-06-14

申请号：US14514704

申请日：2014-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo-Jae Park ,  Hyun-Suk Chun

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/02126 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11916 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/07025 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: The method includes forming an upper layer on a lower layer, forming a metal interconnection in the upper layer, forming a passivation layer exposing a center part of the metal interconnection on the upper layer, forming a buffer pattern exposing the center part of the metal interconnection, and selectively and asymmetrically covering a peripheral region of the metal interconnect and a part of the passivation layer, forming a wrapping pattern covering the buffer pattern and exposing the center part of the metal interconnection on the passivation layer, and forming a pad pattern on the center part of the metal interconnection.

Abstract translation: 该方法包括在下层上形成上层，在上层形成金属互连，形成钝化层，暴露上层金属互连的中心部分，形成露出金属互连中心部分的缓冲图案 并且选择性地和不对称地覆盖金属互连的周边区域和钝化层的一部分，形成覆盖缓冲图案的包覆图案，并使钝化层上的金属互连的中心部分露出，并在 中心部分金属互连。