-
公开(公告)号:US10014267B2
公开(公告)日:2018-07-03
申请号:US15145231
申请日:2016-05-03
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yong-Sang Cho , Sang-Woo Pae , Hyun-Suk Chun , Young-Seok Jung
IPC: H01L23/00 , H01L23/58 , H01L23/31 , H01L23/525
CPC classification number: H01L24/02 , H01L23/3114 , H01L23/525 , H01L23/585 , H01L24/05 , H01L24/13 , H01L24/94 , H01L2224/02235 , H01L2224/0235 , H01L2224/0237 , H01L2224/02379 , H01L2224/02381 , H01L2224/0239 , H01L2224/0401 , H01L2224/05569 , H01L2224/13024 , H01L2224/131 , H01L2224/94 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/141 , H01L2924/351 , H01L2924/00012 , H01L2924/014 , H01L2224/0231 , H01L2224/11
Abstract: A semiconductor device comprises a semiconductor chip which includes at least one gate structure on a substrate, the gate structure including a first region, a second region different from the first region, and a third region between the first and the second region, a first redistribution layer on a top surface of the semiconductor chip, the first redistribution layer configured to electrically connect a first electrode pad of the semiconductor chip to a first solder ball and overlap the first region of the gate structure, a second redistribution layer on the top surface of the semiconductor chip, the second redistribution layer configured to electrically connect a second electrode pad of the semiconductor chip to a second solder ball and overlap the second region of the gate structure such that the third region is exposed, and an insulating layer on the first redistribution layer and the second redistribution layer.
-
公开(公告)号:US10347576B2
公开(公告)日:2019-07-09
申请号:US15709947
申请日:2017-09-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kwang-Won Choi , Sang-Woo Pae , Seong-Won Jeong , Min-Jae Kwon , Da-Hye Min , Jin-Chul Park , Jae-Won Chang
IPC: H01L23/498 , H01L23/053 , H01L23/13 , H01L23/20 , H01L23/24 , H01L23/31 , H01L23/00 , H01L23/16 , H01L21/56
Abstract: A semiconductor package includes a package substrate, the package substrate including a conductive plate, an insulating plate on the conductive plate, the insulating plate including a mounting region and a peripheral region surrounding the mounting region, and at least one capillary channel in the peripheral region, a semiconductor chip on the mounting region of the insulating plate, and a molding member on the insulating plate to cover the semiconductor chip, a portion of the molding member being in the at least one capillary channel.
-
公开(公告)号:US10298214B2
公开(公告)日:2019-05-21
申请号:US15584448
申请日:2017-05-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hye-Won Shim , Dong-Uk Park , Phil-Jae Jeon , Sang-Woo Pae , Da Ahn
Abstract: A clock switch device includes a control circuit and a tri-state buffer. The control circuit deactivates an output enable signal when a frequency of a clock signal varies and activates the output enable signal when the frequency of the clock signal is maintained without change. The tri-state buffer maintains an output electrode at a high impedance state when the output enable signal is deactivated and buffers the clock signal and outputs the buffered clock signal through the output electrode as an output clock signal when the output enable signal is activated.
-
公开(公告)号:US20180006034A1
公开(公告)日:2018-01-04
申请号:US15698978
申请日:2017-09-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyong-Taek Lee , Sang-Woo Pae , Hye-Jin Kim , June-Kyun Park , Hyun-Woo Lee
IPC: H01L27/092 , H01L27/088 , H01L21/8234 , H01L27/11
CPC classification number: H01L27/0922 , G06F17/5022 , G06F17/5045 , G06F17/505 , G06F17/5081 , H01L21/823462 , H01L27/088 , H01L27/1104
Abstract: A system and method may determine the operating parameters, such as voltages, of MOS transistors within a circuit design by testing or simulation, for example and may identify a MOS transistor operating with its drain voltage higher than its gate voltage in the circuit. The design system and method may substitute a smaller transistor, having a high-k dielectric layer, for the original transistor in the circuit design.
-
公开(公告)号:US10276571B2
公开(公告)日:2019-04-30
申请号:US15698978
申请日:2017-09-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyong-Taek Lee , Sang-Woo Pae , Hye-Jin Kim , June-Kyun Park , Hyun-Woo Lee
IPC: G06F17/50 , H01L27/092 , H01L27/088 , H01L27/00 , H01L27/11 , H01L21/8234
Abstract: A system and method may determine the operating parameters, such as voltages, of MOS transistors within a circuit design by testing or simulation, for example and may identify a MOS transistor operating with its drain voltage higher than its gate voltage in the circuit. The design system and method may substitute a smaller transistor, having a high-k dielectric layer, for the original transistor in the circuit design.
-
公开(公告)号:US10191099B2
公开(公告)日:2019-01-29
申请号:US15244780
申请日:2016-08-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Soon-Young Lee , Sang-Woo Pae
IPC: G01R31/00 , G01R31/3181 , G01R31/303
Abstract: A semiconductor test device includes an actuator holding a radiation source and adjusting a distance between the radiation source and a sample, and a controller controlling an operation of the actuator and calculating a soft error rate (SER) of the sample based on the distance between the radiation source and the sample. The controller calculates a first distance between the radiation source and the sample at which the SER of the sample becomes zero, and calculates a metal-to-dielectric ratio of the sample based on the first distance.
-
公开(公告)号:US20170082682A1
公开(公告)日:2017-03-23
申请号:US15244780
申请日:2016-08-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: SOON-YOUNG LEE , Sang-Woo Pae
IPC: G01R31/28
CPC classification number: G01R31/002 , G01R31/303 , G01R31/31816
Abstract: A semiconductor test device includes an actuator holding a radiation source and adjusting a distance between the radiation source and a sample, and a controller controlling an operation of the actuator and calculating a soft error rate (SER) of the sample based on the distance between the radiation source and the sample. The controller calculates a first distance between the radiation source and the sample at which the SER of the sample becomes zero, and calculates a metal-to-dielectric ratio of the sample based on the first distance.
-
-
-
-
-
-