公开(公告)号：US20230162784A1

公开(公告)日：2023-05-25

申请号：US17881187

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmyung KANG ,  Hoyoung TANG ,  Inhak LEE ,  Sangyeop BAECK ,  Dongwook SEO

IPC: G11C11/4096 ,  G11C11/4094 ,  G11C11/4074

CPC classification number: G11C11/4096 ,  G11C11/4094 ,  G11C11/4074

Abstract: A memory device includes a bit cell array including a plurality of bit cells connected to a first auxiliary line to which a cell power voltage is supplied; a write driver configured to apply a bit line voltage corresponding to write data to a bit line extending in a column direction of the bit cell array during a write operation; and a write auxiliary circuit connected to the first auxiliary line and a second auxiliary line extending in parallel to the first auxiliary line, and configured to lower a cell power voltage for a first bit cell spaced apart from the write driver during the write operation, wherein the cell power voltage is supplied to the first auxiliary line through the second auxiliary line, and in sequence from the first bit cell to a second bit cell adjacent to the write driver through the first auxiliary line.

公开(公告)号：US20240243038A1

公开(公告)日：2024-07-18

申请号：US18515384

申请日：2023-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eojin LEE ,  Taehyung KIM ,  Hoyoung TANG ,  Jaehyun LIM

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/7851 ,  H10B10/125

Abstract: An integrated circuit includes: a substrate including a cell area and a dummy area, wherein a plurality of cells are arranged in the cell area; a front-side wiring layer arranged over a front surface of the substrate in a vertical direction, wherein the front-side wiring layer includes a first pattern extending in a first direction across the cell area and the dummy area and a second pattern extending in a second direction intersecting the first direction and contacting the first pattern; a through via overlapping the front-side wiring layer in the vertical direction in the dummy area and passing through the substrate; and a back-side wiring layer arranged on a rear surface of the substrate, wherein the back-side wiring layer is connected through the through via and the front-side wiring layer to at least one transistor included in the plurality of cells.

公开(公告)号：US20250079310A1

公开(公告)日：2025-03-06

申请号：US18806236

申请日：2024-08-15

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Hoyoung TANG ,  Taehyung KIM

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit includes: a backside wiring layer on a back side of a substrate, the backside wiring layer including a first backside pattern and a second backside pattern isolated from each other; and a power gating switch on a front side of the substrate, the power gating switch connected to the first and second backside patterns. The power gating switch includes: a first source/drain region connected to the first backside pattern, and configured to receive a first supply voltage from the first backside pattern; a gate line structure configured to receive a power gating signal; and a second source/drain region connected to the second backside pattern, and configured to receive a power signal from the first source/drain region based on the power gating signal.

公开(公告)号：US20240349497A1

公开(公告)日：2024-10-17

申请号：US18637013

申请日：2024-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suk YOUN ,  Taehyung KIM ,  Hoyoung TANG

IPC: H10B20/00

CPC classification number: H10B20/387

Abstract: An integrated circuit includes a read only memory (ROM) cell which includes an on-cell. The on-cell includes: a first source/drain region and a second source/drain region; a frontside contact between the first source/drain region and a bit line on a front side of the on-cell; and a backside contact between the second source/drain region and a power line on a back side of the on-cell. The bit line is configured to provide a bit line signal to the on-cell, and the power line is configured to provide a power supply voltage signal to the on-cell. The bit line and the power line are vertically aligned with each other.

公开(公告)号：US20240312493A1

公开(公告)日：2024-09-19

申请号：US18606790

申请日：2024-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngrok PARK ,  Hoyoung TANG ,  Taehyung KIM

IPC: G11C5/06 ,  G11C11/418 ,  H01L23/522 ,  H01L23/528 ,  H10B10/00

CPC classification number: G11C5/063 ,  G11C11/418 ,  H01L23/5226 ,  H01L23/5283 ,  H10B10/12

Abstract: An integrated circuit includes a substrate; a bit cell array including bit cells on the substrate; a frontside wiring layer above the substrate in a vertical direction with respect to a front side of the substrate, the frontside wiring layer including local word lines connected to the bit cells; a row decoder configured to provide word line signals for driving the bit cell array; a backside wiring layer on a backside of the substrate, the backside wiring layer including backside wiring lines configured to receive the word line signals from the row decoder; and a word line rebuffer configured to provide the word line signals received from the backside wiring lines to the local word lines.