公开(公告)号：US20180182463A1

公开(公告)日：2018-06-28

申请号：US15391006

申请日：2016-12-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  Sarath Puthenthermadam ,  Chris Yip

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G06F3/06

CPC classification number: G11C16/3427 ,  G06F3/0619 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0679 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459

Abstract: A non-volatile memory system implements a multi-pass programming process that includes separately programming groups of memory cells in a common block by performing programming for memory cells that are connected to two adjacent word lines and are part of a first group of memory cells followed by performing programming for other memory cells that are also connected to the two adjacent word lines and are part of a second group of memory cells.

公开(公告)号：US09711231B1

公开(公告)日：2017-07-18

申请号：US15191898

申请日：2016-06-24

Applicant: SanDisk Technologies LLC

Inventor： Chris Yip ,  Philip Reusswig ,  Nian Niles Yang ,  Grishma Shah ,  Abuzer Azo Dogan ,  Biswajit Ray ,  Mohan Dunga ,  Joanna Lai ,  Changyuan Chen

IPC: G11C16/26 ,  G11C16/28 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C16/28 ,  G06F11/1048 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/30 ,  G11C16/32

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. In one aspect, read voltages are set and optimized based on a time period since a last sensing operation. A timing device such as an n-bit digital counter may be provided for each block of memory cells to track the time. The counter is set to all 1's when the device is powered on. When a sensing operation occurs, the counter is periodically incremented based on a clock. When a next read operation occurs, the value of the counter is cross-referenced to an optimal set of read voltage shifts. Each block of cells may have its own counter, where the counters are incremented using a local or global clock.

公开(公告)号：US10068656B2

公开(公告)日：2018-09-04

申请号：US15391006

申请日：2016-12-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  Sarath Puthenthermadam ,  Chris Yip

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G06F3/06

CPC classification number: G11C16/3427 ,  G06F3/0619 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0679 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459

Abstract: A non-volatile memory system implements a multi-pass programming process that includes separately programming groups of memory cells in a common block by performing programming for memory cells that are connected to two adjacent word lines and are part of a first group of memory cells followed by performing programming for other memory cells that are also connected to the two adjacent word lines and are part of a second group of memory cells.