公开(公告)号：US10381327B2

公开(公告)日：2019-08-13

申请号：US15287344

申请日：2016-10-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Venkatesh P. Ramachandra ,  Michael Mostovoy ,  Hem Takiar ,  Gokul Kumar ,  Vinayak Ghatawade

IPC: H01L25/065 ,  H01L25/18 ,  G11C7/10 ,  G11C7/22 ,  G11C29/00 ,  G11C7/06 ,  G06F13/40 ,  G06F13/42 ,  G11C5/04 ,  G11C5/06

Abstract: A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled to another wide I/O interface of another memory die of the plurality of memory dies. The interface circuit is physically separate from the memory dies. The interface circuit includes a first interface and a second interface. The first interface comprises a wide I/O interface electrically coupled to a wide I/O interface of at least one of the memory dies of the plurality of memory dies. The second interface is a narrow I/O interface configured to communicate with an external circuit.

公开(公告)号：US10468073B2

公开(公告)日：2019-11-05

申请号：US15858496

申请日：2017-12-29

Applicant: SanDisk Technologies LLC

Inventor： John Thomas Contreras ,  Gokul Kumar

IPC: G11C5/06 ,  H01L25/065 ,  H01L23/522 ,  H01L23/00 ,  G11C5/04

Abstract: An apparatus may include a controller die configured to communicate with a plurality of dies via a transmission line. The controller die may be configured to transmit a signal on the transmission line to a target die of the plurality of dies, or the target die may transmit a signal on the transmission line. The transmission may be dependent on an end die of the plurality of dies setting an end-die termination resistance to a low level. In situations where the target memory is receiving the signal, the target die may set target an on-die termination resistance to a high level. In situations where the target memory die is transmitting the signal, the target die may set an on-die termination resistance to a low level.

公开(公告)号：US20190206450A1

公开(公告)日：2019-07-04

申请号：US15858496

申请日：2017-12-29

Applicant: SanDisk Technologies LLC

Inventor： John Thomas Contreras ,  Gokul Kumar

IPC: G11C5/06 ,  H01L25/065 ,  H01L23/522 ,  H01L23/00

Abstract: An apparatus may include a controller die configured to communicate with a plurality of dies via a transmission line. The controller die may be configured to transmit a signal on the transmission line to a target die of the plurality of dies, or the target die may transmit a signal on the transmission line. The transmission may be dependent on an end die of the plurality of dies setting an end-die termination resistance to a low level. In situations where the target memory is receiving the signal, the target die may set target an on-die termination resistance to a high level. In situations where the target memory die is transmitting the signal, the target die may set an on-die termination resistance to a low level.

公开(公告)号：US20180102344A1

公开(公告)日：2018-04-12

申请号：US15287344

申请日：2016-10-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Venkatesh P. Ramachandra ,  Michael Mostovoy ,  Hem Takiar ,  Gokul Kumar ,  Vinayak Ghatawade

IPC: H01L25/065 ,  H01L25/18 ,  G11C7/10 ,  G11C7/22 ,  G11C29/00 ,  G11C7/06

CPC classification number: H01L25/0657 ,  G06F13/4018 ,  G06F13/4234 ,  G11C5/04 ,  G11C5/063 ,  G11C5/066 ,  G11C7/065 ,  G11C7/10 ,  G11C7/22 ,  G11C29/781 ,  G11C2207/105 ,  G11C2207/108 ,  H01L25/18 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled to another wide I/O interface of another memory die of the plurality of memory dies. The interface circuit is physically separate from the memory dies. The interface circuit includes a first interface and a second interface. The first interface comprises a wide I/O interface electrically coupled to a wide I/O interface of at least one of the memory dies of the plurality of memory dies. The second interface is a narrow I/O interface configured to communicate with an external circuit.

公开(公告)号：US10249592B2

公开(公告)日：2019-04-02

申请号：US15898604

申请日：2018-02-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michael Mostovoy ,  Gokul Kumar ,  Ning Ye ,  Hem Takiar ,  Venkatesh P. Ramachandra ,  Vinayak Ghatawade ,  Chih-Chin Liao

IPC: H01L21/78 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065

Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.

公开(公告)号：US20180174996A1

公开(公告)日：2018-06-21

申请号：US15898604

申请日：2018-02-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michael Mostovoy ,  Gokul Kumar ,  Ning Ye ,  Hem Takiar ,  Venkatesh P. Ramachandra ,  Vinayak Ghatawade ,  Chih-Chin Liao

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L21/78

CPC classification number: H01L24/49 ,  H01L21/56 ,  H01L21/78 ,  H01L24/06 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0612 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48499 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/78301 ,  H01L2924/00014 ,  H01L2924/1436 ,  H01L2924/14511 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/01079 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.

公开(公告)号：US09899347B1

公开(公告)日：2018-02-20

申请号：US15454194

申请日：2017-03-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michael Mostovoy ,  Gokul Kumar ,  Ning Ye ,  Hem Takiar ,  Venkatesh P. Ramachandra ,  Vinayak Ghatawade ,  Chih-Chin Liao

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L24/49 ,  H01L21/56 ,  H01L21/78 ,  H01L24/06 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0612 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48499 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/78301 ,  H01L2924/00014 ,  H01L2924/1436 ,  H01L2924/14511 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/01079 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.