公开(公告)号：US11973026B2

公开(公告)日：2024-04-30

申请号：US17684922

申请日：2022-03-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki Sano ,  Koichi Ito

IPC: H10B41/27 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings located in a memory array region and vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and laterally-isolated contact via assemblies located in a contact region. Each of the laterally-isolated contact via assemblies includes a contact via structure contacting a top surface of a respective one of the electrically conductive layers and an insulating spacer laterally surrounding the contact via structure and having an outer surface having a corrugated vertical cross-sectional profile in which first portions of the insulating spacer located at levels of the electrically conductive layers laterally protrude outward relative to second portions of the insulating spacer located at levels of the insulating layers.

公开(公告)号：US10971514B2

公开(公告)日：2021-04-06

申请号：US16276996

申请日：2019-02-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka Otsu ,  Kei Nozawa ,  Yashushi Doda ,  Naoto Hojo ,  Yoshinobu Tanaka ,  Koichi Ito ,  Zhiwei Chen ,  Yusuke Ikawa ,  Takeshi Kawamura ,  Ryoichi Ehara

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L21/311 ,  H01L21/28 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526

Abstract: A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers. The dielectric support pillar structures may be formed before or after formation of stepped surfaces in the alternating stack.

公开(公告)号：US11495612B2

公开(公告)日：2022-11-08

申请号：US16918463

申请日：2020-07-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshinobu Tanaka ,  Koichi Ito ,  Hideaki Hasegawa ,  Akihiro Tobioka ,  Sung Tae Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11529

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

公开(公告)号：US11450679B2

公开(公告)日：2022-09-20

申请号：US16918493

申请日：2020-07-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshinobu Tanaka ,  Koichi Ito ,  Hideaki Hasegawa ,  Akihiro Tobioka ,  Sung Tae Lee

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11529 ,  H01L21/311 ,  H01L27/11573

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

公开(公告)号：US10957706B2

公开(公告)日：2021-03-23

申请号：US16276952

申请日：2019-02-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka Otsu ,  Kei Nozawa ,  Yashushi Doda ,  Naoto Hojo ,  Yoshinobu Tanaka ,  Koichi Ito

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L21/311 ,  H01L21/28 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526

Abstract: A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers. The dielectric support pillar structures may be formed before or after formation of stepped surfaces in the alternating stack.

公开(公告)号：US10797035B1

公开(公告)日：2020-10-06

申请号：US16372908

申请日：2019-04-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki Sano ,  Takashi Yamaha ,  Koichi Ito ,  Ikue Yokomizo ,  Ryo Hiramatsu ,  Kazuto Watanabe ,  Katsuya Kato ,  Hajime Yamamoto ,  Hiroshi Sasaki

IPC: H01L25/18 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

Abstract: A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.

公开(公告)号：US10790296B1

公开(公告)日：2020-09-29

申请号：US16417913

申请日：2019-05-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi Yamaha ,  Katsuya Kato ,  Kazuto Watanabe ,  Hajime Yamamoto ,  Michiaki Sano ,  Koichi Ito ,  Ikue Yokomizo ,  Ryo Hiramatsu ,  Hiroshi Sasaki

IPC: H01L29/792 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11551

Abstract: A bonded structure may be formed by measuring die areas of first semiconductor dies on a wafer at a measurement temperature, generating a two-dimensional map of local target temperatures that are estimated to thermally adjust a die area of each of the first semiconductor dies to a target die area, loading the wafer to a bonding apparatus comprising at least one temperature sensor, and iteratively bonding a plurality of second semiconductor dies to a respective one of the first semiconductor dies by sequentially adjusting a temperature of the wafer to a local target temperature of a respective first semiconductor die that is bonded to a respective one of the second semiconductor dies. An apparatus for forming such a bonded structure may include a computer, a chuck for holding the wafer, a die attachment unit, and a temperature control mechanism.

公开(公告)号：US11133252B2

公开(公告)日：2021-09-28

申请号：US16782307

申请日：2020-02-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Ito ,  Yoshinobu Tanaka ,  Hirofumi Tokita

IPC: H01L23/528 ,  G11C8/14 ,  H01L27/11519 ,  H01L21/02 ,  H01L21/28 ,  H01L21/225 ,  H01L27/11524 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556

Abstract: A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, such that the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, iteratively performing a first set of non-offset layer patterning processing steps at least twice to form a first part of a terrace region including a set of stepped surfaces which extend in a first horizontal direction, and performing a second set of offset layer patterning processing steps to form a second part of the terrace region and to form a stepped vertical cross-sectional profile for patterned surfaces of the vertically alternating sequence along a second horizontal direction which is perpendicular to the first horizontal direction.