公开(公告)号：US10269620B2

公开(公告)日：2019-04-23

申请号：US15274451

申请日：2016-09-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Zhenyu Lu ,  Hiroyuki Ogawa ,  Daxin Mao ,  Kensuke Yamaguchi ,  Sung Tae Lee ,  Yao-sheng Lee ,  Johann Alsmeier

IPC: H01L27/115 ,  H01L21/768 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11548

Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.

公开(公告)号：US11495612B2

公开(公告)日：2022-11-08

申请号：US16918463

申请日：2020-07-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshinobu Tanaka ,  Koichi Ito ,  Hideaki Hasegawa ,  Akihiro Tobioka ,  Sung Tae Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11529

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

公开(公告)号：US11450679B2

公开(公告)日：2022-09-20

申请号：US16918493

申请日：2020-07-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshinobu Tanaka ,  Koichi Ito ,  Hideaki Hasegawa ,  Akihiro Tobioka ,  Sung Tae Lee

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11529 ,  H01L21/311 ,  H01L27/11573

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

公开(公告)号：US09673304B1

公开(公告)日：2017-06-06

申请号：US15210915

申请日：2016-07-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki Sano ,  Akira Nakada ,  Tetsuya Yamada ,  Manabu Hayashi ,  Takashi Matsubara ,  Sung Tae Lee ,  Akio Nishida

IPC: H01L29/66 ,  H01L27/115 ,  H01L29/792 ,  H01L29/788 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2454 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

Abstract: A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material on a sidewall of the hole, forming a local bit line in the hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.