公开(公告)号：US20190371380A1

公开(公告)日：2019-12-05

申请号：US16000816

申请日：2018-06-05

Applicant: SanDisk Technologies LLC

Inventor： Yadhu Vamshi Vancha ,  James Hart ,  Jeffrey Koon Yee Lee ,  Tz-Yi Liu ,  Ali Al-Shamma ,  Yingchang Chen

IPC: G11C8/08 ,  G11C7/12 ,  G11C7/08

Abstract: One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.

公开(公告)号：US10254967B2

公开(公告)日：2019-04-09

申请号：US15402180

申请日：2017-01-09

Applicant: SanDisk Technologies LLC

Inventor： Jingwen Ouyang ,  Tz-Yi Liu ,  Henry Zhang ,  Yingchang Chen

IPC: G11C16/34 ,  G11C16/10 ,  G06F3/06

Abstract: Apparatuses, systems, and methods are disclosed for controlling a data path for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a memory core. A memory core includes an array of non-volatile memory cells and an internal data pipeline. A memory die includes a buffer that stores data associated with storage operations for a memory core. A memory die includes an internal controller that communicates with a memory core to initiate storage operations. An internal controller may delay initiating a storage operation in response to determining that an internal data pipeline and a buffer are both full.

公开(公告)号：US10074427B2

公开(公告)日：2018-09-11

申请号：US14539033

申请日：2014-11-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Idan Alrod ,  Noam Presman ,  Ariel Navon ,  Tz-Yi Liu ,  Tianhong Yan

IPC: G11C13/00 ,  G11C7/10

CPC classification number: G11C13/0097 ,  G11C7/1006 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0085 ,  G11C2213/77

Abstract: A method includes, in a data storage device including a resistive memory, receiving, from an external device, an erase command to erase a portion of the resistive memory. The method further includes storing shaped data at the portion of the resistive memory responsive to the erase command. Shaped data is configured to control an amount of leakage current during a read and/or write operation at one or more storage elements that are adjacent to at least one storage element of the portion of the resistive memory.

公开(公告)号：US10803912B2

公开(公告)日：2020-10-13

申请号：US16251484

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yadhu Vamshi Vancha ,  Ali Al-Shamma ,  Yingchang Chen ,  Jeffrey Lee ,  Tz-Yi Liu

IPC: G11C7/06 ,  G11C11/16

Abstract: A circuit or associated system or apparatus includes a first transistor, a second transistor, a first switch, a second switch, a first current source, and a third switch. The first transistor is configured to sample a first current of a control line. The second transistor is configured to apply a second current to the control line. The second transistor is also configured to match the second current to the first current. The first switch is connected in series between a control terminal of the first transistor and a control terminal of the second transistor. The second switch is connected in series between the second transistor and the control line. The third switch is connected in series between the first current source and the control line.

公开(公告)号：US20200273512A1

公开(公告)日：2020-08-27

申请号：US16281699

申请日：2019-02-21

Applicant: SanDisk Technologies LLC

Inventor： Christopher J. Petti ,  Tz-Yi Liu ,  Ali Al-Shamma ,  Yoocharn Jeon

IPC: G11C11/16 ,  H01L27/22

Abstract: Magnetic random-access memory (MRAM) circuits are provided herein. In one example implementation, an MRAM circuit includes control circuitry coupled to a magnetic tunnel junction (MTJ) element in series with a selector element. This control circuitry is configured to adjust current through the selector element when the selector element is in a conductive state. The circuit also includes a compensation circuitry configured to compensate for a offset voltage across the selector element in the conductive state based on adjustments to the current through the selector element. An output circuit is also configured to report a magnetization state of the MTJ element.

公开(公告)号：US20200234743A1

公开(公告)日：2020-07-23

申请号：US16251484

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yadhu Vamshi Vancha ,  Ali Al-Shamma ,  Yingchang Chen ,  Jeffrey Lee ,  Tz-Yi Liu

IPC: G11C7/06 ,  G11C11/16

Abstract: A circuit or associated system or apparatus includes a first transistor, a second transistor, a first switch, a second switch, a first current source, and a third switch. The first transistor is configured to sample a first current of a control line. The second transistor is configured to apply a second current to the control line. The second transistor is also configured to match the second current to the first current. The first switch is connected in series between a control terminal of the first transistor and a control terminal of the second transistor. The second switch is connected in series between the second transistor and the control line. The third switch is connected in series between the first current source and the control line.

公开(公告)号：US09947401B1

公开(公告)日：2018-04-17

申请号：US15388154

申请日：2016-12-22

Applicant: SanDisk Technologies LLC

Inventor： Ariel Navon ,  Tz-Yi Liu ,  Eran Sharon ,  Alexander Bazarsky ,  Judah Hahn ,  Alon Eyal ,  Omer Fainzilber

IPC: G11C19/08 ,  G11C13/00 ,  G06F11/07 ,  G06F11/30 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C13/0069 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/1068 ,  G06F11/3034 ,  G06F11/3062 ,  G11C13/0023 ,  G11C13/0038 ,  G11C29/52 ,  G11C2013/0078

Abstract: Technology is described for keeping current (e.g., peak power supply current or ICC) in a non-volatile memory system within a target while maintaining high throughput. Programming conditions are adaptively changed at the sub-codeword level in order to keep power supply current of the memory system within a target. In one embodiment, a chunk of data that corresponds to a sub-codeword is written while consuming lower than normal programming current in order to keep power supply current within a target. The relatively low programming current may increase the expected raw BER. However, other portions of the codeword can be written with a higher than normal programming current, which results in a lower expected bit raw error rate for the memory cells that store that portion.

公开(公告)号：US20170199668A1

公开(公告)日：2017-07-13

申请号：US15402180

申请日：2017-01-09

Applicant: SanDisk Technologies LLC

Inventor： Jingwen Ouyang ,  Tz-Yi Liu ,  Henry Zhang ,  Yingchang Chen

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0679 ,  G06F3/0688

Abstract: Apparatuses, systems, and methods are disclosed for controlling a data path for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a memory core. A memory core includes an array of non-volatile memory cells and an internal data pipeline. A memory die includes a buffer that stores data associated with storage operations for a memory core. A memory die includes an internal controller that communicates with a memory core to initiate storage operations. An internal controller may delay initiating a storage operation in response to determining that an internal data pipeline and a buffer are both full.

公开(公告)号：US11031059B2

公开(公告)日：2021-06-08

申请号：US16281699

申请日：2019-02-21

Applicant: SanDisk Technologies LLC

Inventor： Christopher J. Petti ,  Tz-Yi Liu ,  Ali Al-Shamma ,  Yoocharn Jeon

IPC: G11C11/16 ,  H01L27/22

Abstract: Magnetic random-access memory (MRAM) circuits are provided herein. In one example implementation, an MRAM circuit includes control circuitry coupled to a magnetic tunnel junction (MTJ) element in series with a selector element. This control circuitry is configured to adjust current through the selector element when the selector element is in a conductive state. The circuit also includes a compensation circuitry configured to compensate for a offset voltage across the selector element in the conductive state based on adjustments to the current through the selector element. An output circuit is also configured to report a magnetization state of the MTJ element.

公开(公告)号：US10734048B2

公开(公告)日：2020-08-04

申请号：US16000816

申请日：2018-06-05

Applicant: SanDisk Technologies LLC

Inventor： Yadhu Vamshi Vancha ,  James Hart ,  Jeffrey Koon Yee Lee ,  Tz-Yi Liu ,  Ali Al-Shamma ,  Yingchang Chen

IPC: G11C8/08 ,  G11C7/08 ,  G11C7/12

Abstract: One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.