SENSING MEMORY CELLS USING ARRAY CONTROL LINES

    公开(公告)号:US20190371380A1

    公开(公告)日:2019-12-05

    申请号:US16000816

    申请日:2018-06-05

    Abstract: One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.

    Data path control for non-volatile memory

    公开(公告)号:US10254967B2

    公开(公告)日:2019-04-09

    申请号:US15402180

    申请日:2017-01-09

    Abstract: Apparatuses, systems, and methods are disclosed for controlling a data path for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a memory core. A memory core includes an array of non-volatile memory cells and an internal data pipeline. A memory die includes a buffer that stores data associated with storage operations for a memory core. A memory die includes an internal controller that communicates with a memory core to initiate storage operations. An internal controller may delay initiating a storage operation in response to determining that an internal data pipeline and a buffer are both full.

    Fast voltage compensation without feedback

    公开(公告)号:US10803912B2

    公开(公告)日:2020-10-13

    申请号:US16251484

    申请日:2019-01-18

    Abstract: A circuit or associated system or apparatus includes a first transistor, a second transistor, a first switch, a second switch, a first current source, and a third switch. The first transistor is configured to sample a first current of a control line. The second transistor is configured to apply a second current to the control line. The second transistor is also configured to match the second current to the first current. The first switch is connected in series between a control terminal of the first transistor and a control terminal of the second transistor. The second switch is connected in series between the second transistor and the control line. The third switch is connected in series between the first current source and the control line.

    MAGNETIC RANDOM-ACCESS MEMORY WITH SELECTOR VOLTAGE COMPENSATION

    公开(公告)号:US20200273512A1

    公开(公告)日:2020-08-27

    申请号:US16281699

    申请日:2019-02-21

    Abstract: Magnetic random-access memory (MRAM) circuits are provided herein. In one example implementation, an MRAM circuit includes control circuitry coupled to a magnetic tunnel junction (MTJ) element in series with a selector element. This control circuitry is configured to adjust current through the selector element when the selector element is in a conductive state. The circuit also includes a compensation circuitry configured to compensate for a offset voltage across the selector element in the conductive state based on adjustments to the current through the selector element. An output circuit is also configured to report a magnetization state of the MTJ element.

    FAST VOLTAGE COMPENSATION WITHOUT FEEDBACK
    6.
    发明申请

    公开(公告)号:US20200234743A1

    公开(公告)日:2020-07-23

    申请号:US16251484

    申请日:2019-01-18

    Abstract: A circuit or associated system or apparatus includes a first transistor, a second transistor, a first switch, a second switch, a first current source, and a third switch. The first transistor is configured to sample a first current of a control line. The second transistor is configured to apply a second current to the control line. The second transistor is also configured to match the second current to the first current. The first switch is connected in series between a control terminal of the first transistor and a control terminal of the second transistor. The second switch is connected in series between the second transistor and the control line. The third switch is connected in series between the first current source and the control line.

    DATA PATH CONTROL FOR NON-VOLATILE MEMORY
    8.
    发明申请

    公开(公告)号:US20170199668A1

    公开(公告)日:2017-07-13

    申请号:US15402180

    申请日:2017-01-09

    CPC classification number: G06F3/061 G06F3/0655 G06F3/0679 G06F3/0688

    Abstract: Apparatuses, systems, and methods are disclosed for controlling a data path for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a memory core. A memory core includes an array of non-volatile memory cells and an internal data pipeline. A memory die includes a buffer that stores data associated with storage operations for a memory core. A memory die includes an internal controller that communicates with a memory core to initiate storage operations. An internal controller may delay initiating a storage operation in response to determining that an internal data pipeline and a buffer are both full.

    Magnetic random-access memory with selector voltage compensation

    公开(公告)号:US11031059B2

    公开(公告)日:2021-06-08

    申请号:US16281699

    申请日:2019-02-21

    Abstract: Magnetic random-access memory (MRAM) circuits are provided herein. In one example implementation, an MRAM circuit includes control circuitry coupled to a magnetic tunnel junction (MTJ) element in series with a selector element. This control circuitry is configured to adjust current through the selector element when the selector element is in a conductive state. The circuit also includes a compensation circuitry configured to compensate for a offset voltage across the selector element in the conductive state based on adjustments to the current through the selector element. An output circuit is also configured to report a magnetization state of the MTJ element.

    Sensing memory cells using array control lines

    公开(公告)号:US10734048B2

    公开(公告)日:2020-08-04

    申请号:US16000816

    申请日:2018-06-05

    Abstract: One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.

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