公开(公告)号：US11449431B2

公开(公告)日：2022-09-20

申请号：US15608127

申请日：2017-05-30

Applicant: Seagate Technology LLC

Inventor： Mark Ish ,  Timothy Canepa ,  David S. Ebsen

IPC: G06F12/0888 ,  G06F12/02 ,  G06F9/4401

Abstract: A data storage device may consist of a non-volatile memory having rewritable in-place memory cells each with a read-write asymmetry. The non-volatile memory can store boot data that is subsequently loaded by a selection module of the data storage device. The selection module may bypass a memory buffer of the data storage device to load the boot data.

公开(公告)号：US10754555B2

公开(公告)日：2020-08-25

申请号：US16201733

申请日：2018-11-27

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Jeffrey Munsil ,  Jackson Ellis ,  Mark Ish

IPC: G06F12/02 ,  G06F3/06

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

公开(公告)号：US10558380B2

公开(公告)日：2020-02-11

申请号：US15232682

申请日：2016-08-09

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： David S. Ebsen ,  Kevin A. Gomez ,  Mark Ish ,  Daniel J. Benjamin

IPC: G06F3/06

Abstract: Systems and methods for active power management are described. In one embodiment, the systems and methods include obtaining power dissipation metrics for a plurality of components under one or more operating scenarios, generating a reference dissipation model based on the power dissipation metrics of the plurality of components, and implementing the reference dissipation model in a storage system to make component scheduling decisions in relation to power management of the storage system. In some embodiments, the storage system includes any combination of a hard disk drive, a solid state drive, a hybrid drive, and a system of multiple storage drives.

公开(公告)号：US10310975B2

公开(公告)日：2019-06-04

申请号：US15152374

申请日：2016-05-11

Applicant: Seagate Technology LLC

Inventor： Shashank Nemawarkar ,  Balakrishnan Sundararaman ,  Mark Ish ,  Siddhartha Kumar Panda ,  Bagavathy Raj Arunachalam

IPC: G06F11/07 ,  G06F12/0804 ,  G06F3/06 ,  G06F12/0868 ,  G06F11/14 ,  G06F1/32 ,  G06F1/3234 ,  G06F11/20

Abstract: The disclosed technology provides for selection of a subset of available non-volatile memory devices in an array to receive a dirty cache data of a volatile cache responsive to detection of a power failure. In one implementation, the selection of the non-volatile memory devices is based on one or more predictive power parameters usable to estimate a time remaining during which a reserve power supply can support a cache offload to the selected subset of devices.

公开(公告)号：US10275361B2

公开(公告)日：2019-04-30

申请号：US15609758

申请日：2017-05-31

Applicant: Seagate Technology LLC

Inventor： Mark Ish ,  Steven S. Williams ,  Jeffrey Munsil

IPC: G06F12/10

Abstract: Apparatus and method for managing namespaces in a Non-Volatile Memory Express (NVMe) controller environment. A non-volatile memory (NVM) is arranged to store map units (MUs) as addressable data blocks in one or more namespaces. A forward map has a sequence of map unit address (MUA) entries that correlate each of the MUs with the physical locations in the NVM. The MUA entries are grouped into immediately adjacent, contiguous ranges for each of the namespaces. A base MUA array identifies the address, within the forward map, of the beginning MUA entry for each namespace. A new namespace may be added by appending a new range of the MUA entries to the forward map immediate following the last MUA entry, and by adding a new entry to the base MUA array to identify the address, within the forward map, of the beginning MUA entry for the new namespace.

公开(公告)号：US20180341594A1

公开(公告)日：2018-11-29

申请号：US15606502

申请日：2017-05-26

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Jeffrey Munsil ,  Jackson Ellis ,  Mark Ish

IPC: G06F12/1009 ,  G06F3/06

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

公开(公告)号：US20170242794A1

公开(公告)日：2017-08-24

申请号：US15048080

申请日：2016-02-19

Applicant: Seagate Technology LLC

Inventor： Horia Cristian Simionescu ,  Balakrishnan Sundararaman ,  Shashank Nemawarkar ,  Larry Stephen King ,  Mark Ish ,  Shailendra Aulakh

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/10

CPC classification number: G06F12/0806 ,  G06F12/0804 ,  G06F12/0895 ,  G06F12/1018 ,  G06F12/1081 ,  G06F12/122 ,  G06F2212/1024 ,  G06F2212/604 ,  G06F2212/621 ,  G06F2212/656

Abstract: In response to a cacheable write request from a host, physical cache locations are allocated from a free list, and the data blocks are written to those cache locations without regard to whether any read requests to the corresponding logical addresses are pending. After the data has been written, and again without regard to whether any read requests are pending against the corresponding logical addresses, metadata is updated to associate the cache locations with the logical addresses. A count of data access requests pending against each cache location having valid data is maintained, and a cache location is only returned to the free list when the count indicates no data access requests are pending against the cache location.

公开(公告)号：US11630779B2

公开(公告)日：2023-04-18

申请号：US17528977

申请日：2021-11-17

Applicant: Seagate Technology LLC

Inventor： Nitin Satishchandra Kabra ,  Jackson Ellis ,  Niranjan Anant Pol ,  Mark Ish

IPC: G06F12/0873 ,  G06F12/128 ,  G06F12/02

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

公开(公告)号：US10739996B1

公开(公告)日：2020-08-11

申请号：US15213298

申请日：2016-07-18

Applicant: Seagate Technology LLC

Inventor： David Scott Ebsen ,  Kevin A Gomez ,  Mark Ish ,  Daniel John Benjamin ,  Robert Wayne Moss

IPC: G06F16/00 ,  G06F3/06 ,  G06F16/17 ,  G06F16/11 ,  G06F16/2455

Abstract: Systems and methods are disclosed for enhanced garbage collection operations at a memory device. The enhanced garbage collection may include selecting data and blocks to garbage collect to improve device performance. Data may be copied and reorganized according to a data stream via which the data was received, or data and blocks may be evaluated for garbage collection based on other access efficiency metrics. Data may be selected for collection based on sequentiality of the data, host access patterns, or other factors. Processing of host commands may be throttled based on a determined amount of work to garbage collect a plurality of blocks, in order to limit variability in host command throughput over a time period.

公开(公告)号：US20190095341A1

公开(公告)日：2019-03-28

申请号：US16201733

申请日：2018-11-27

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Jeffrey Munsil ,  Jackson Ellis ,  Mark Ish

IPC: G06F12/1009 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7208

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.