公开(公告)号：US20230369029A1

公开(公告)日：2023-11-16

申请号：US18298551

申请日：2023-04-11

Applicant: SEMES CO., LTD.

Inventor： Hyoungkyu SON ,  Jaewoong Sim ,  Donguk Kim ,  Yunsang Kim ,  Inhoe Kim

IPC: H01J37/32

CPC classification number: H01J37/32642 ,  H01J37/32697 ,  H01J37/32724 ,  H01J37/32082 ,  H01J2237/002 ,  H01J2237/2007

Abstract: A substrate processing device is provided. The substrate processing device includes: a substrate supporter configured to support a substrate; a heating ring horizontally surrounding the substrate supporter; and an edge ring horizontally surrounding the heating ring and configured to cover a top surface of the heating ring.

公开(公告)号：US20240064967A1

公开(公告)日：2024-02-22

申请号：US18206490

申请日：2023-06-06

Applicant: SEMES CO., LTD.

Inventor： Chengyeh Hsu ,  Thomas Jongwan Kwon ,  Yunsang Kim ,  Haewon Choi

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/488 ,  H10B12/315

Abstract: A semiconductor device includes bit lines each extending in a first direction on a substrate and spaced apart from each other in a second direction, semiconductor patterns disposed on each of the bit lines and including a first semiconductor pattern disposed on a first bit line, and a second semiconductor pattern arranged to be offset in the second direction from the first semiconductor pattern on the first bit line, word lines each extending in the second direction and surrounding a sidewall of each of the semiconductor patterns, the word lines including a first word line extending in the second direction and surrounding the first semiconductor pattern, and a second word line spaced apart in the first direction from the first word line and extending in the second direction while surrounding the second semiconductor pattern, and storage nodes respectively disposed on the semiconductor patterns.

公开(公告)号：US20230377894A1

公开(公告)日：2023-11-23

申请号：US18304754

申请日：2023-04-21

Applicant: SEMES CO., LTD.

Inventor： Minyoung Kim ,  Hanglim Lee ,  Yunsang Kim

IPC: H01L21/306 ,  H01L21/768 ,  H01L23/48 ,  H01L21/67

CPC classification number: H01L21/30608 ,  H01L21/76898 ,  H01L23/481 ,  H01L21/6708 ,  H01L21/67086 ,  H01L23/535

Abstract: Disclosed is a method of forming a semiconductor device, the method including: forming at least one metal catalyst layer on a rear surface of a semiconductor substrate, on which at least one buried power rail for power transfer is formed, to be at least partially aligned with the buried power rail; and forming at least one rear surface via hole by supplying an etchant to the semiconductor substrate so that the semiconductor substrate between the metal catalyst layer and the buried power rail is anisotropically etched while the metal catalyst layer descends to an inside of the semiconductor substrate using metal-assisted chemical etching (MACE).