公开(公告)号：US20220077282A1

公开(公告)日：2022-03-10

申请号：US17016708

申请日：2020-09-10

Applicant: Semiconductor Components Industries, LLC

Inventor： Gary Horst Loechelt ,  Balaji Padmanabhan ,  Dean E. Probst ,  Tirthajyoti Sarkar ,  Prasad Venkatraman ,  Muh-Ling Ger

IPC: H01L29/06 ,  H01L29/78

Abstract: An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.

公开(公告)号：US11481532B2

公开(公告)日：2022-10-25

申请号：US17076039

申请日：2020-10-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： James Joseph Victory ,  Thomas Neyer ,  YunPeng Xiao ,  Hyeongwoo Jang ,  Peter Dingenen ,  Vaclav Valenta ,  Tirthajyoti Sarkar ,  Mehrdad Baghaie Yazdi ,  Christopher Lawrence Rexer ,  Stanley Benczkowski ,  Thierry Bordignon ,  Wai Lun Chu ,  Roman Sickaruk

IPC: G06F30/367 ,  G06F30/31 ,  G06F30/392 ,  G06F30/398 ,  G06N3/04 ,  G06N3/08 ,  G06F119/08 ,  G06F111/02 ,  G06F117/12

Abstract: Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.

公开(公告)号：US11411077B2

公开(公告)日：2022-08-09

申请号：US17016708

申请日：2020-09-10

Applicant: Semiconductor Components Industries, LLC

Inventor： Gary Horst Loechelt ,  Balaji Padmanabhan ,  Dean E. Probst ,  Tirthajyoti Sarkar ,  Prasad Venkatraman ,  Muh-Ling Ger

IPC: H01L29/06 ,  H01L29/78

Abstract: An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.

公开(公告)号：US20220077290A1

公开(公告)日：2022-03-10

申请号：US17016682

申请日：2020-09-10

Applicant: Semiconductor Components Industries, LLC

Inventor： Gary Horst Loechelt ,  Balaji Padmanabhan ,  Dean E. Probst ,  Tirthajyoti Sarkar ,  Prasad Venkatraman ,  Muh-Ling Ger

IPC: H01L29/40 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739

Abstract: A circuit and physical structure can help to counteract non-linear COSS associated with power transistors that operate at higher switching speeds and lower RDSON. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.

公开(公告)号：US11621331B2

公开(公告)日：2023-04-04

申请号：US17016682

申请日：2020-09-10

Applicant: Semiconductor Components Industries, LLC

Inventor： Gary Horst Loechelt ,  Balaji Padmanabhan ,  Dean E. Probst ,  Tirthajyoti Sarkar ,  Prasad Venkatraman ,  Muh-Ling Ger

IPC: H01L29/40 ,  H01L23/528 ,  H01L29/739 ,  H01L29/10 ,  H01L29/06

Abstract: A circuit and physical structure can help to counteract non-linear COSS associated with power transistors that operate at higher switching speeds and lower RDSON. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.

公开(公告)号：US10396216B2

公开(公告)日：2019-08-27

申请号：US15585839

申请日：2017-05-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yi Su ,  Ashok Challa ,  Tirthajyoti Sarkar ,  Min Kyung Ko

IPC: H01L29/47 ,  H01L29/78 ,  H01L29/872 ,  H01L29/06 ,  H01L29/40

Abstract: In one general aspect, a device can include a first trench disposed in a semiconductor region, a second trench disposed in the semiconductor region, and a recess disposed in the semiconductor region between the first trench and the second trench. The recess has a sidewall and a bottom surface. The device also includes a Schottky interface along a sidewall of the recess and the bottom surface of the recess excludes a Schottky interface.