公开(公告)号：US11133381B2

公开(公告)日：2021-09-28

申请号：US15959479

申请日：2018-04-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Shengling Deng ,  Dean E. Probst ,  Zia Hossain

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L29/868 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

Abstract: In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.

公开(公告)号：US11621331B2

公开(公告)日：2023-04-04

申请号：US17016682

申请日：2020-09-10

Applicant: Semiconductor Components Industries, LLC

Inventor： Gary Horst Loechelt ,  Balaji Padmanabhan ,  Dean E. Probst ,  Tirthajyoti Sarkar ,  Prasad Venkatraman ,  Muh-Ling Ger

IPC: H01L29/40 ,  H01L23/528 ,  H01L29/739 ,  H01L29/10 ,  H01L29/06

Abstract: A circuit and physical structure can help to counteract non-linear COSS associated with power transistors that operate at higher switching speeds and lower RDSON. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.

公开(公告)号：US11227946B2

公开(公告)日：2022-01-18

申请号：US16825945

申请日：2020-03-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Prasad Venkatraman ,  Dean E. Probst

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: A device has an active area made of an array of first type of device cells and a gate or shield contact area made of an array of a second type of device cells that are laid out at a wider pitch than the array of first type of device cells. Each first type of device cell in the active area includes a trench that contains a gate electrode and an adjoining mesa that contains the drain, source, body, and channel regions of the device. Each second type of device cell in the gate or shield contact area includes a trench that is wider and deeper than the trench in the first type device cell.

公开(公告)号：US11075148B2

公开(公告)日：2021-07-27

申请号：US16675525

申请日：2019-11-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter Gambino ,  David T. Price ,  Jeffery A. Neuls ,  Dean E. Probst ,  Santosh Menon ,  Peter A. Burke ,  Bigildis Dosdos

IPC: H01L23/00 ,  H01L23/495 ,  H01L25/00 ,  H01L25/11

Abstract: A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.

公开(公告)号：US12278266B2

公开(公告)日：2025-04-15

申请号：US18469780

申请日：2023-09-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Shengling Deng ,  Dean E. Probst ,  Zia Hossain

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/868

Abstract: In a general aspect, a method can include forming well region of one conductivity type in a semiconductor region of another conductivity type An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The method can further include forming at least one dielectric region in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.

公开(公告)号：US12051967B2

公开(公告)日：2024-07-30

申请号：US17806597

申请日：2022-06-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Dean E. Probst ,  Joseph Andrew Yedinak ,  Balaji Padmanabhan ,  Peter A Burke ,  Jeffery A. Neuls ,  Ashok Challa

IPC: H02M1/34 ,  H01L27/07

CPC classification number: H02M1/34 ,  H01L27/0727

Abstract: In some aspects, the techniques described herein relate to a circuit including: a metal-oxide semiconductor field-effect transistor (MOSFET) including a gate, a source, and a drain; and a snubber circuit coupled between the drain and the source, the snubber circuit including: a diode having a cathode and an anode, the cathode being coupled with the drain; a capacitor having a first terminal coupled with the anode, and a second terminal coupled with the source; and a resistor having a first terminal coupled with the anode and the first terminal of the capacitor, and a second terminal coupled with the source.

公开(公告)号：US11742420B2

公开(公告)日：2023-08-29

申请号：US17534084

申请日：2021-11-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Dean E. Probst ,  Peter A. Burke ,  Prasad Venkatraman

IPC: H01L29/78 ,  H01L21/765 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/7811 ,  H01L21/765 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/42368 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: In one embodiment, a semiconductor device is formed having a plurality of active trenches formed within an active region of the semiconductor device. A first insulator is formed along at least a portion of sidewalls of each active trench. A perimeter termination trench is formed that surrounds the active region. The perimeter termination trench is formed having a first sidewall that is adjacent the active region and a second sidewall that is opposite the first sidewall. An insulator is formed along the second sidewall that has a thickness is greater than an insulator that is formed along the first sidewall.

公开(公告)号：US20220077282A1

公开(公告)日：2022-03-10

申请号：US17016708

申请日：2020-09-10

Applicant: Semiconductor Components Industries, LLC

Inventor： Gary Horst Loechelt ,  Balaji Padmanabhan ,  Dean E. Probst ,  Tirthajyoti Sarkar ,  Prasad Venkatraman ,  Muh-Ling Ger

IPC: H01L29/06 ,  H01L29/78

Abstract: An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.

公开(公告)号：US11411077B2

公开(公告)日：2022-08-09

申请号：US17016708

申请日：2020-09-10

Applicant: Semiconductor Components Industries, LLC

Inventor： Gary Horst Loechelt ,  Balaji Padmanabhan ,  Dean E. Probst ,  Tirthajyoti Sarkar ,  Prasad Venkatraman ,  Muh-Ling Ger

IPC: H01L29/06 ,  H01L29/78

Abstract: An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.

公开(公告)号：US20220077290A1

公开(公告)日：2022-03-10

申请号：US17016682

申请日：2020-09-10

Applicant: Semiconductor Components Industries, LLC

Inventor： Gary Horst Loechelt ,  Balaji Padmanabhan ,  Dean E. Probst ,  Tirthajyoti Sarkar ,  Prasad Venkatraman ,  Muh-Ling Ger

IPC: H01L29/40 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739

Abstract: A circuit and physical structure can help to counteract non-linear COSS associated with power transistors that operate at higher switching speeds and lower RDSON. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.