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公开(公告)号：US11411077B2
公开(公告)日：2022-08-09
申请号：US17016708
申请日：2020-09-10
发明人： Gary Horst Loechelt , Balaji Padmanabhan , Dean E. Probst , Tirthajyoti Sarkar , Prasad Venkatraman , Muh-Ling Ger
摘要： An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.
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公开(公告)号：US20220077290A1
公开(公告)日：2022-03-10
申请号：US17016682
申请日：2020-09-10
发明人： Gary Horst Loechelt , Balaji Padmanabhan , Dean E. Probst , Tirthajyoti Sarkar , Prasad Venkatraman , Muh-Ling Ger
IPC分类号： H01L29/40 , H01L23/528 , H01L29/06 , H01L29/10 , H01L29/739
摘要： A circuit and physical structure can help to counteract non-linear COSS associated with power transistors that operate at higher switching speeds and lower RDSON. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.
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公开(公告)号：US11257916B2
公开(公告)日：2022-02-22
申请号：US16450149
申请日：2019-06-24
发明人： Balaji Padmanabhan , Prasad Venkatraman , Zia Hossain , Donald Zaremba , Gordon M. Grivna , Alexander Young
IPC分类号： H01L29/423 , H01L29/78 , H01L29/792 , H01L27/24 , H01L21/762
摘要： Systems and methods of the disclosed embodiments include an electronic device that has a gate electrode for supplying a gate voltage, a source, a drain, and a channel doped to enable a current to flow from the drain to the source when a voltage is applied to the gate electrode. The electronic device may also include a gate insulator between the channel and the gate electrode. The gate insulator may include a first gate insulator section including a first thickness, and a second gate insulator section including a second thickness that is less than the first thickness. The gate insulator sections thereby improve the safe operating area by enabling the current to flow through the second gate insulator section at a lower voltage than the first gate insulator section.
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公开(公告)号：US10276713B2
公开(公告)日：2019-04-30
申请号：US15487517
申请日：2017-04-14
发明人： Chun-Li Liu , Balaji Padmanabhan , Ali Salih , Peter Moens
IPC分类号： H01L29/66 , H01L29/06 , H01L29/20 , H01L29/10 , H01L29/778 , H01L21/74 , H01L29/78 , H01L21/768 , H01L21/762 , H01L29/417 , H01L21/76 , H01L21/763 , H01L21/02
摘要： In accordance with an embodiment, a semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.
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公开(公告)号：US10218350B2
公开(公告)日：2019-02-26
申请号：US15215310
申请日：2016-07-20
IPC分类号： H03K17/16
摘要： A circuit can include a first transistor including a source and a gate; a second transistor including a drain and a gate, wherein the source of the first transistor is coupled to the drain of the second transistor; and a switchable element. In one embodiment, a first current-carrying terminal of the switchable element is coupled to the gate of the first transistor, and a second current-carrying terminal of the switchable element is coupled to the gate of the second transistor. In another embodiment, the switchable element is coupled to the gate of the first transistor and includes a first selectable terminal of the switchable element coupled to a source of the second transistor, and a second selectable terminal of the switchable element coupled to the gate of the second transistor. In a particular embodiment, the circuit can be a cascode circuit.
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公开(公告)号：US09917184B2
公开(公告)日：2018-03-13
申请号：US15209578
申请日：2016-07-13
IPC分类号： H01L21/336 , H01L31/062 , H01L27/01 , H01L29/78 , H01L29/66 , H01L29/10 , H01L27/088 , H01L29/423 , H01L29/06 , H01L29/40
CPC分类号： H01L29/7813 , H01L27/0727 , H01L27/088 , H01L29/0623 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L29/7805
摘要： Embodiments include a method and structure to that provide a clamping structure in an integrated semiconductor device. In accordance with an embodiment, the method includes forming trenches in a semiconductor material and forming a shield electrode in a portion of at least one of the trenches. A clamping structure is formed adjacent to a trench. The clamping structure has an electrode that may be electrically connected to a source region of the integrated semiconductor device. In accordance with another embodiment, an impedance element is formed in a trench.
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公开(公告)号：US09620443B2
公开(公告)日：2017-04-11
申请号：US15208703
申请日：2016-07-13
IPC分类号： H01L23/495 , H01L23/31 , H01L21/48 , H01L21/56
CPC分类号： H01L23/49575 , H01L21/4825 , H01L21/4882 , H01L23/3735 , H01L23/4951 , H01L23/4952 , H01L23/49524 , H01L23/49531 , H01L23/49548 , H01L23/49562 , H01L23/49568 , H01L2224/0603 , H01L2224/16245 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2224/37099
摘要： In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead and a second lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support.
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公开(公告)号：US20170025339A1
公开(公告)日：2017-01-26
申请号：US15207626
申请日：2016-07-12
发明人： Chun-Li Liu , Ali Salih , Balaji Padmanabhan , Mingjiao Liu
IPC分类号： H01L23/495 , H01L25/18 , H01L23/00 , H01L23/14
CPC分类号： H01L23/49575 , H01L23/3735 , H01L23/4952 , H01L23/49524 , H01L23/49562 , H01L23/49861 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/18 , H01L29/16 , H01L29/2003 , H01L2224/37099 , H01L2224/40105 , H01L2224/40245 , H01L2224/48091 , H01L2224/48105 , H01L2224/48145 , H01L2224/48245 , H01L2224/49112 , H01L2224/49176 , H01L2224/49177 , H01L2224/73221 , H01L2924/00014 , H01L2924/1203 , H01L2924/1306 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012 , H01L2224/85399
摘要： A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.
摘要翻译： 半导体部件包括具有与其一体形成的引线的支撑件。 绝缘金属基板安装在支撑体的表面上，半导体芯片安装在绝缘金属基板上。 基于III-N的半导体芯片安装到绝缘金属基板上，其中III-N基半导体芯片具有栅极焊盘，漏极接合焊盘和源极焊盘。 硅基半导体芯片安装在基于III-N的半导体芯片上。 根据实施例，硅基半导体芯片包括具有栅极接合焊盘，漏极接合焊盘和源极焊盘的器件。 III-N型半导体芯片的漏极接合焊盘可以结合到衬底或引线上。 根据另一个实施例，硅基半导体芯片是二极管。
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公开(公告)号：US20170025338A1
公开(公告)日：2017-01-26
申请号：US15204604
申请日：2016-07-07
发明人： Balaji Padmanabhan , Prasad Venkatraman , Ali Salih , Chun-Li Liu
IPC分类号： H01L23/495 , H01L21/48 , H01L25/00 , H01L25/07
CPC分类号： H01L23/49575 , H01L23/49524 , H01L23/49531 , H01L23/49562 , H01L25/074 , H01L25/50 , H01L2224/0603 , H01L2224/16245 , H01L2224/40 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2224/37099
摘要： In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support.
摘要翻译： 根据实施例，半导体部件包括具有第一和第二器件接收结构的支撑件。 由III-N半导体材料配置的半导体器件耦合到支撑件，其中半导体器件具有相对的表面。 第一接合焊盘从第一表面的第一部分延伸，第二接合焊盘从第一表面的第二部分延伸，并且第三接合焊盘从第一表面的第三部分延伸。 第一接合焊盘耦合到第一器件接收部分，漏极接合焊盘耦合到第二器件接收部分，并且第三接合焊盘耦合到第三引线。 根据另一实施例，一种方法包括将包括III-N半导体衬底材料的半导体芯片耦合到支撑体。
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公开(公告)号：US20170025337A1
公开(公告)日：2017-01-26
申请号：US15204261
申请日：2016-07-07
IPC分类号： H01L23/495 , H01L29/772 , H01L29/20 , H01L21/48 , H01L29/861
CPC分类号： H01L23/49575 , H01L21/4853 , H01L23/3735 , H01L23/49524 , H01L23/49531 , H01L23/49562 , H01L24/06 , H01L24/40 , H01L24/48 , H01L24/73 , H01L25/072 , H01L29/2003 , H01L29/772 , H01L2224/0603 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73221 , H01L2924/00014 , H01L2224/37099 , H01L2224/45099
摘要： In accordance with an embodiment, a semiconductor component includes a support and a plurality of leads. An insulated metal substrate having a first portion and a second portion bonded to the support. A semiconductor chip comprising a III-N semiconductor material is bonded to the first portion of the insulated metal substrate and a first electrical interconnect is coupled between a drain bond pad the first portion of the insulated metal substrate. A second semiconductor chip is bonded to the first electrical interconnect. A second electrical interconnect coupled between a lead of the plurality of leads and the second semiconductor chip. In accordance with another embodiment, a method of manufacturing a semiconductor component includes coupling a first semiconductor chip to a first electrically conductive layer and coupling a second semiconductor chip to a second electrically conductive layer.
摘要翻译： 根据实施例，半导体部件包括支撑件和多个引线。 绝缘金属基板，具有第一部分和第二部分结合到支撑体上。 包含III-N半导体材料的半导体芯片被接合到绝缘金属基板的第一部分，并且第一电互连件耦合在绝缘金属基板的第一部分的漏极接合焊盘之间。 第二半导体芯片被结合到第一电互连。 耦合在所述多个引线的引线和所述第二半导体芯片之间的第二电互连。 根据另一实施例，制造半导体部件的方法包括将第一半导体芯片耦合到第一导电层并将第二半导体芯片耦合到第二导电层。
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