公开(公告)号：US20250035703A1

公开(公告)日：2025-01-30

申请号：US18770967

申请日：2024-07-12

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Ankur BAL ,  Aradhana KUMARI

IPC: G01R31/3185

Abstract: An integrated circuit is provided. For example, an integrated circuit comprises a functional data path and a scan-data path. At least a portion of the scan-data path is separate from the functional data path. The portion of the scan-data path which is separate from the functional data path comprises a combined gating/delay element for preventing a scan-data signal from reaching any elements downstream of the combined gating/delay element during a scan mode and for providing some or all of a desired signal delay in the portion of the scan-data path which is separate from the functional data path.

公开(公告)号：US20240039545A1

公开(公告)日：2024-02-01

申请号：US18348899

申请日：2023-07-07

Applicant: STMicroelectronics International N.V.

Inventor： Rupesh SINGH ,  Ankur BAL

IPC: H03L7/195 ,  H03L7/199 ,  H03K3/356

CPC classification number: H03L7/195 ,  H03L7/199 ,  H03K3/356026

Abstract: Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.

公开(公告)号：US20220345149A1

公开(公告)日：2022-10-27

申请号：US17723225

申请日：2022-04-18

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Abhishek JAIN ,  Sharad GUPTA

IPC: H03M3/00

Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

公开(公告)号：US20220321111A1

公开(公告)日：2022-10-06

申请号：US17673214

申请日：2022-02-16

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL

IPC: H03K5/02

Abstract: A delay circuit applies a one sample delay to a first digital sinusoid signal and outputs a delayed digital sinusoid signal. The first digital sinusoid signal and the delayed digital sinusoid signal are then added to each other by an adder circuit to generate an added digital sinusoid signal. A gain scaling circuit applies a scaling factor to the added digital sinusoid signal to generate a second digital sinusoid signal. Samples of the first and second digital sinusoid signals are alternately selected by a multiplexing circuit to generate a third digital sinusoid signal having twice as many samples as the first digital sinusoid signal over a same sinusoid period.

公开(公告)号：US20210343319A1

公开(公告)日：2021-11-04

申请号：US17374304

申请日：2021-07-13

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Rupesh SINGH ,  Vivek TRIPATHI

IPC: G11C7/10 ,  H03L7/107 ,  G11C7/22 ,  H03M1/00 ,  G11C7/04

Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.

公开(公告)号：US20240364347A1

公开(公告)日：2024-10-31

申请号：US18623331

申请日：2024-04-01

Applicant: STMicroelectronics International N.V.

Inventor： Rupesh SINGH ,  Ankur BAL ,  Kirtiman Singh RATHORE

IPC: H03L7/00 ,  H03K3/037 ,  H03K5/1534 ,  H03K19/20

CPC classification number: H03L7/00 ,  H03K3/037 ,  H03K5/1534 ,  H03K19/20

Abstract: A first latching circuit has a reset function controlled by a reset signal and configured to latch a logic state in response to a first edge of a clock signal to generate a first output signal. A second latching circuit has a reset function controlled by that reset signal and configured to latch a logic state in response to a second edge of that clock signal to generate a second output signal. The first and second edges are opposite edges. A combinatorial logic circuit logically combines the first and second output signals to generate a logic output signal. A third latching circuit has a reset function controlled by that reset signal and configured to latch the logic output signal in response to the second edge of that clock signal to generate a reset synchronization control signal.

公开(公告)号：US20240235573A1

公开(公告)日：2024-07-11

申请号：US18396542

申请日：2023-12-26

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Abhishek JAIN ,  Sharad GUPTA

IPC: H03M3/00

CPC classification number: H03M3/378 ,  H03M3/46 ,  H03M3/496

Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multibit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

公开(公告)号：US20230299751A1

公开(公告)日：2023-09-21

申请号：US18185130

申请日：2023-03-16

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Gaurav AGGARWAL

IPC: H03H17/06 ,  H03H17/02

CPC classification number: H03H17/0657 ,  H03H17/0275

Abstract: A method generates a delayed signal based on an input signal, and applies vector magnitude scaling to the delayed signal, generating one or more vector magnitude scaled signals. The input signal is added to the one or more vector magnitude scaled signals, generating one or more phase-shifted signals. Compensation scaling is applied to the one or more phase-shifted signals, generating one or more compensated signals. The input signal and the one or more compensated signals are combined, generating an interpolated output signal. The method may be implemented by a device or a system.

公开(公告)号：US20230054364A1

公开(公告)日：2023-02-23

申请号：US17982242

申请日：2022-11-07

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Sharad GUPTA

IPC: H03M1/08 ,  H03M1/10 ,  H03M1/06

Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.

公开(公告)号：US20220188203A1

公开(公告)日：2022-06-16

申请号：US17682167

申请日：2022-02-28

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Rupesh SINGH

IPC: G06F11/22 ,  G06F13/42

Abstract: A serial-connection is tested by transmitting a PRBS generated using a kth-order monic-polynomial from transmission-circuitry to reception-circuitry, and determining operation is proper based upon the PRBS received. The PRBS is formed by generating x intermediate-words of the PRBS, x being a result of an integer-divide between a total number of bits in the PRBS and a bit-width of a serializer that transmits the PRBS, generating a leading-word of the PRBS as having first y-bits of the PRBS as its LSBs, y being based upon a modulo-divide between the total number of bits in the PRBS and x, and generating a trailing-word of the PRBS as having last z-bits of the PRBS as its MSBs, z being based upon a difference between a result of the modulo-divide and y. The PRBS is transmitted sequentially as the leading-word of the PRBS, the intermediate-words of the PRBS, and the trailing-word of the PRBS.