公开(公告)号：US20140375358A1

公开(公告)日：2014-12-25

申请号：US13922483

申请日：2013-06-20

Applicant: STMicroelectronics International N.V.

Inventor： Surendra Kumar

IPC: H03K19/0175

CPC classification number: H03K19/017509 ,  H03K19/00315 ,  H03K19/018521

Abstract: A circuit includes a first input transistor and a first voltage divider coupled to a source of the first input transistor and a second input transistor and a second voltage divider coupled to a source of the second input transistor. A first set of series connected transistors include a first transistor with a gate coupled to the first input transistor source and a second transistor with a gate coupled to a tap of the first voltage divider. A second set of series connected transistors include a third transistor with a gate coupled to the second input transistor source and a fourth transistor with a gate coupled to a tap of the second voltage divider. An output is coupled to the sources of the first and second input transistors. The first and second sets are coupled to one of the first input transistor drain or second input transistor drain.

Abstract translation: 电路包括耦合到第一输入晶体管的源极的第一输入晶体管和第一分压器以及耦合到第二输入晶体管的源极的第二输入晶体管和第二分压器。 第一组串联晶体管包括具有耦合到第一输入晶体管源的栅极的第一晶体管和耦合到第一分压器的抽头的栅极的第二晶体管。 第二组串联连接的晶体管包括具有耦合到第二输入晶体管源的栅极的第三晶体管和具有耦合到第二分压器的抽头的栅极的第四晶体管。 输出耦合到第一和第二输入晶体管的源极。 第一和第二组耦合到第一输入晶体管漏极或第二输入晶体管漏极之一。

公开(公告)号：US09696351B2

公开(公告)日：2017-07-04

申请号：US14585357

申请日：2014-12-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Daljeet Kumar ,  Tapas Nandy ,  Surendra Kumar

IPC: G01R19/04 ,  G01R19/25

CPC classification number: G01R19/04 ,  G01R19/2503

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

公开(公告)号：US10024888B2

公开(公告)日：2018-07-17

申请号：US15618269

申请日：2017-06-09

Applicant: STMicroelectronics International N.V.

Inventor： Daljeet Kumar ,  Tapas Nandy ,  Surendra Kumar

IPC: G01R19/04 ,  G01R19/25

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

公开(公告)号：US08922256B1

公开(公告)日：2014-12-30

申请号：US13971373

申请日：2013-08-20

Applicant: STMicroelectronics International N.V.

Inventor： Surendra Kumar

IPC: H03K3/00

CPC classification number: H03K17/687 ,  H03K17/0422

Abstract: An apparatus includes a number of current steering switches and a power controller. A current source is coupled to the current steering switches and to the power controller. The current source is controlled to provide a first voltage to the current steering switches. The apparatus also includes a number of pre-drivers. The power controller is configured to provide a second voltage to the plurality of pre-drivers. The second voltage is dependent on the first voltage.

Abstract translation: 一种装置包括多个当前的转向开关和功率控制器。 电流源耦合到当前的转向开关和功率控制器。 控制电流源以向当前的转向开关提供第一电压。 该装置还包括若干预驱动器。 功率控制器被配置为向多个预驱动器提供第二电压。 第二电压取决于第一电压。

公开(公告)号：US20130127537A1

公开(公告)日：2013-05-23

申请号：US13735114

申请日：2013-01-07

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tapas Nandy ,  Surendra Kumar

IPC: H03F3/45

CPC classification number: H03F3/45071 ,  H03F1/0266 ,  H03F3/45192 ,  H03F3/45632 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2203/45302 ,  H03F2203/45354 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45434 ,  H03F2203/45446 ,  H03F2203/45702

Abstract: A circuit includes a differential amplifier having a folded cascode architecture with a pair of cascode transistors. A sensing circuit senses a common mode input voltage of a differential input signal applied to the differential amplifier. A bias generator circuit generates a bias voltage for application to the pair of cascode transistors in the folded cascode architecture. The bias generator circuit is connected to an output of the sensing circuit such that the generated bias voltage has a value which is dependent on the sensed common mode input voltage. This dependence stabilizes a common mode output voltage from the differential amplifier in response to changes in the common mode input voltage.

Abstract translation: 电路包括具有折叠共源共栅结构的差分放大器和一对共源共栅晶体管。 感测电路感测施加到差分放大器的差分输入信号的共模输入电压。 偏置发生器电路在折叠共源共栅结构中产生用于施加到该对共源共栅晶体管的偏置电压。 偏置发生器电路连接到感测电路的输出，使得产生的偏置电压具有取决于感测到的共模输入电压的值。 这种依赖性响应于共模输入电压的变化而稳定来自差分放大器的共模输出电压。

公开(公告)号：US08975929B2

公开(公告)日：2015-03-10

申请号：US13922483

申请日：2013-06-20

Applicant: STMicroelectronics International N.V.

Inventor： Surendra Kumar

IPC: H03B1/00 ,  H03K19/0175

CPC classification number: H03K19/017509 ,  H03K19/00315 ,  H03K19/018521

Abstract: A circuit includes a first input transistor and a first voltage divider coupled to a source of the first input transistor and a second input transistor and a second voltage divider coupled to a source of the second input transistor. A first set of series connected transistors include a first transistor with a gate coupled to the first input transistor source and a second transistor with a gate coupled to a tap of the first voltage divider. A second set of series connected transistors include a third transistor with a gate coupled to the second input transistor source and a fourth transistor with a gate coupled to a tap of the second voltage divider. An output is coupled to the sources of the first and second input transistors. The first and second sets are coupled to one of the first input transistor drain or second input transistor drain.

Abstract translation: 电路包括耦合到第一输入晶体管的源极的第一输入晶体管和第一分压器以及耦合到第二输入晶体管的源极的第二输入晶体管和第二分压器。 第一组串联晶体管包括具有耦合到第一输入晶体管源的栅极的第一晶体管和耦合到第一分压器的抽头的栅极的第二晶体管。 第二组串联连接的晶体管包括具有耦合到第二输入晶体管源的栅极的第三晶体管和具有耦合到第二分压器的抽头的栅极的第四晶体管。 输出耦合到第一和第二输入晶体管的源极。 第一和第二组耦合到第一输入晶体管漏极或第二输入晶体管漏极之一。

公开(公告)号：US08502603B2

公开(公告)日：2013-08-06

申请号：US13735114

申请日：2013-01-07

Applicant: STMicroelectronics International N.V.

Inventor： Tapas Nandy ,  Surendra Kumar

IPC: H03F3/45

CPC classification number: H03F3/45071 ,  H03F1/0266 ,  H03F3/45192 ,  H03F3/45632 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2203/45302 ,  H03F2203/45354 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45434 ,  H03F2203/45446 ,  H03F2203/45702

Abstract: A circuit includes a differential amplifier having a folded cascode architecture with a pair of cascode transistors. A sensing circuit senses a common mode input voltage of a differential input signal applied to the differential amplifier. A bias generator circuit generates a bias voltage for application to the pair of cascode transistors in the folded cascode architecture. The bias generator circuit is connected to an output of the sensing circuit such that the generated bias voltage has a value which is dependent on the sensed common mode input voltage. This dependence stabilizes a common mode output voltage from the differential amplifier in response to changes in the common mode input voltage.

Abstract translation: 电路包括具有折叠共源共栅结构的差分放大器和一对共源共栅晶体管。 感测电路感测施加到差分放大器的差分输入信号的共模输入电压。 偏置发生器电路在折叠共源共栅结构中产生用于施加到该对共源共栅晶体管的偏置电压。 偏置发生器电路连接到感测电路的输出，使得产生的偏置电压具有取决于感测到的共模输入电压的值。 这种依赖性响应于共模输入电压的变化而稳定来自差分放大器的共模输出电压。

公开(公告)号：US20170276710A1

公开(公告)日：2017-09-28

申请号：US15618269

申请日：2017-06-09

Applicant: STMicroelectronics International N.V.

Inventor： Daljeet Kumar ,  Tapas Nandy ,  Surendra Kumar

IPC: G01R19/04 ,  G01R19/25

CPC classification number: G01R19/04 ,  G01R19/2503

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.