公开(公告)号：US20190267380A1

公开(公告)日：2019-08-29

申请号：US15908575

申请日：2018-02-28

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Fabio DE SANTIS ,  Vikas RANA

IPC: H01L27/105 ,  H01L27/11521 ,  G11C29/00 ,  H01L27/112

Abstract: According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

公开(公告)号：US20230206971A1

公开(公告)日：2023-06-29

申请号：US18175375

申请日：2023-02-27

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Vivek TYAGI ,  Vikas RANA ,  Chantal AURICCHIO ,  Laura CAPECCHI

IPC: G11C7/12 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/4091 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C11/4094 ,  G11C11/4091 ,  G11C7/222

Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.

公开(公告)号：US20200258885A1

公开(公告)日：2020-08-13

申请号：US16863856

申请日：2020-04-30

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Fabio DE SANTIS ,  Vikas RANA

IPC: H01L27/105 ,  H01L27/11521 ,  H01L27/112 ,  G11C29/00 ,  H01L27/11519 ,  H01L27/11558

Abstract: According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

公开(公告)号：US20220165317A1

公开(公告)日：2022-05-26

申请号：US17542203

申请日：2021-12-03

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vivek TYAGI ,  Vikas RANA ,  Chantal AURICCHIO ,  Laura CAPECCHI

IPC: G11C7/12 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/4091 ,  G11C7/22

Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.

公开(公告)号：US20220068400A1

公开(公告)日：2022-03-03

申请号：US17006510

申请日：2020-08-28

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Marco PASOTTI ,  Dario LIVORNESI ,  Roberto BREGOLI ,  Vikas RANA ,  Abhishek MITTAL

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/34

Abstract: An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation.

公开(公告)号：US20210074340A1

公开(公告)日：2021-03-11

申请号：US17010704

申请日：2020-09-02

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Vivek TYAGI ,  Vikas RANA ,  Chantal AURICCHIO ,  Laura CAPECCHI

IPC: G11C7/12 ,  G11C7/06 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094

Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.

公开(公告)号：US20240312495A1

公开(公告)日：2024-09-19

申请号：US18676354

申请日：2024-05-28

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA ,  Arpit VIJAYVERGIA

IPC: G11C7/06 ,  H03K19/20

CPC classification number: G11C7/06 ,  H03K19/20

Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.

公开(公告)号：US20210281172A1

公开(公告)日：2021-09-09

申请号：US17313533

申请日：2021-05-06

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA

IPC: H02M3/07

Abstract: A charge pump includes an intermediate node capacitively coupled to receive a first clock signal oscillating between a ground and positive supply voltage, the intermediate node generating a first signal oscillating between a first and second voltage. A level shifting circuit shifts the first signal in response to a second clock signal to generate a second signal oscillating between first and third voltages. A CMOS switching circuit includes a first transistor having a source coupled to an input, a second transistor having a source coupled to an output and a gate coupled to receive the second signal. A common drain of the CMOS switching circuit is capacitively coupled to receive the first clock signal. When positively pumping, the first voltage is twice the second voltage and the third voltage is ground. When negatively pumping, the first and third voltages are of opposite polarity and the second voltage is ground.

公开(公告)号：US20160315611A1

公开(公告)日：2016-10-27

申请号：US14697461

申请日：2015-04-27

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA ,  Amit CHHABRA

IPC: H03K17/687 ,  H01L23/50 ,  H01L23/34 ,  H01L27/12 ,  H01L27/092

CPC classification number: H03K17/693 ,  H01L27/092 ,  H01L27/1203 ,  H03K17/005 ,  H03K2217/0018

Abstract: An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A body bias voltage generator generates a positive body bias voltage, and a negative body bias voltage in the ground body bias voltage. A multiplexer selectively outputs one of the positive, negative, or ground body bias voltage to the doped well region of the semiconductor substrate based on the temperature of the semiconductor substrate.

Abstract translation: 集成电路管芯包括形成在半导体衬底中的多个晶体管，在半导体衬底的掺杂阱区域上的晶体管的体区。 体偏置电压发生器产生正的体偏置电压和负体偏置电压的接地体偏置电压。 复用器基于半导体衬底的温度，将正，负或接地体偏置电压中的一个选择性地输出到半导体衬底的掺杂阱区。

公开(公告)号：US20140233321A1

公开(公告)日：2014-08-21

申请号：US14266468

申请日：2014-04-30

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA

IPC: G11C16/14 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C8/08 ,  G11C16/06 ,  G11C16/26

Abstract: A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line.

Abstract translation: 字线驱动器包括第一，第二和第三晶体管。 第一晶体管包括由第一组选择信号驱动的栅极端子，由第二子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。 第二晶体管包括由第二组选择信号驱动的栅极端子，由第二子组选择信号驱动的第二导通端子和耦合到字线的第一导电端子。 第三晶体管包括由组选择信号的第三组驱动的栅极端子，由第一子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。