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    Bi-synchronous electronic device with burst indicator and related methods
    1.
    发明授权
    Bi-synchronous electronic device with burst indicator and related methods 有权

    公开(公告)号：US09727306B2

    公开(公告)日：2017-08-08

    申请号：US14508126

    申请日：2014-10-07

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Giuseppe Guarnaccia ,  Salvatore Marco Rosselli

    IPC: G06F5/10

    CPC classification number: G06F5/10 ,  G06F2205/102 ,  G06F2205/106

    Abstract: A bi-synchronous electronic device may include a FIFO memory circuit configured to store data, and a first digital circuit coupled to the FIFO memory circuit and configured to operate based upon a first clock signal and a write pointer, write a data burst to the FIFO memory circuit, thereby causing a jump in the write pointer to a new position, and write a burst indicator associated with the new position in the FIFO memory circuit. The bi-synchronous electronic device may include a second digital circuit coupled to the FIFO memory circuit and configured to operate based upon a second clock signal different from the first clock signal, read from the FIFO memory circuit based upon a read pointer, and synchronize the read pointer to the write pointer based upon the burst indicator.

    Bi-synchronous electronic device and FIFO memory circuit with jump candidates and related methods
    2.
    发明授权
    Bi-synchronous electronic device and FIFO memory circuit with jump candidates and related methods 有权
    双同步电子设备和具有跳转候选和FIFO相关方法的FIFO存储器电路

    公开(公告)号：US09311975B1

    公开(公告)日：2016-04-12

    申请号：US14508321

    申请日：2014-10-07

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Salvatore Marco Rosselli ,  Giuseppe Guarnaccia ,  Ugo Mari

    IPC: G11C7/22 ,  G06F5/06

    CPC classification number: G11C7/222 ,  G06F5/06 ,  G06F5/10 ,  G06F2205/102

    Abstract: A bi-synchronous electronic device may include a FIFO memory circuit, and a first digital circuit coupled to the FIFO memory circuit and configured to operate based upon a first clock signal, and write to the FIFO memory circuit based upon a write pointer. The bi-synchronous electronic device may include second digital circuit coupled to the FIFO memory circuit and configured to operate based upon a second clock signal different from the first clock signal, and read from the FIFO memory circuit based upon a read pointer. The FIFO memory circuit may be configured to detect a jump in the write pointer to a new position, determine jump candidates for the read pointer from a current position, select a jump candidate, and synchronize the read pointer based upon the selected jump candidate.

    Abstract translation: 双同步电子设备可以包括FIFO存储器电路和耦合到FIFO存储器电路并被配置为基于第一时钟信号进行操作的第一数字电路，并且基于写指针写入FIFO存储器电路。 双同步电子设备可以包括耦合到FIFO存储器电路并被配置为基于与第一时钟信号不同的第二时钟信号进行操作的第二数字电路，并且基于读指针从FIFO存储器电路读取。 FIFO存储器电路可以被配置为检测写指针中的跳转到新位置，从当前位置确定读指针的跳转候选，选择跳转候选，并且基于所选择的跳转候选来同步读指针。

    Buffer for ordering out-of-order data, and corresponding integrated circuit and method for managing a buffer
    4.
    发明授权
    Buffer for ordering out-of-order data, and corresponding integrated circuit and method for managing a buffer 有权
    用于排序乱序数据的缓冲器，以及用于管理缓冲器的相应集成电路和方法

    公开(公告)号：US09093133B2

    公开(公告)日：2015-07-28

    申请号：US14143383

    申请日：2013-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Daniele Mangano ,  Salvatore Marco Rosselli ,  Giuseppe Falconeri

    IPC: G11C8/08 ,  G11C7/10 ,  G06F5/10

    CPC classification number: G11C7/1006 ,  G06F5/10 ,  G06F2205/106 ,  G06F2205/123

    Abstract: A buffer for ordering out-of-order data includes a memory with a plurality of memory locations for temporarily storing data and a detection circuit configured for generating a control signal when the memory locations contain valid data. The detection circuit includes a first block configured for generating validity signals that identify the memory locations containing valid data and a search circuit configured for determining a search pointer as a function of the validity signals. In the case where each memory location contains valid data, the search pointer indicates the last memory location. In the case where at least one memory location is still free, the search pointer indicates the first memory location that is free.

    Abstract translation: 用于排序无序数据的缓冲器包括具有用于临时存储数据的多个存储器位置的存储器和被配置为当存储器位置包含有效数据时生成控制信号的检测电路。 检测电路包括被配置用于产生识别包含有效数据的存储位置的有效信号的第一块和被配置为根据有效信号确定搜索指针的搜索电路。 在每个存储器位置包含有效数据的情况下，搜索指针指示最后的存储器位置。 在至少一个存储器位置仍然空闲的情况下，搜索指针指示第一存储器位置是空闲的。

    BINARY-TO-GRAY CONVERSION CIRCUIT, RELATED FIFO MEMORY, INTEGRATED CIRCUIT AND METHOD
    5.
    发明申请
    BINARY-TO-GRAY CONVERSION CIRCUIT, RELATED FIFO MEMORY, INTEGRATED CIRCUIT AND METHOD 审中-公开

    公开(公告)号：US20190265947A1

    公开(公告)日：2019-08-29

    申请号：US16256449

    申请日：2019-01-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Salvatore Marco Rosselli ,  Giuseppe Guarnaccia

    IPC: G06F5/14 ,  G06F13/42

    Abstract: A circuit and method for performing a Binary-to-Gray conversion are disclosed. A first binary signal represents a target value and a second binary signal is stored in a register. A set of binary candidate values are determined where the respective Gray equivalent of each binary candidate value has a Hamming distance of one from the Gray equivalent of the second binary value. One of the binary candidate values is selected as a function of the first binary signal and the second binary signal. The selected binary candidate value is provided at input to the register. An encoded signal is generated by determining the Gray encoded equivalent of the selected binary candidate value.

    BUFFER FOR ORDERING OUT-OF-ORDER DATA, AND CORRESPONDING INTEGRATED CIRCUIT AND METHOD FOR MANAGING A BUFFER
    6.
    发明申请
    BUFFER FOR ORDERING OUT-OF-ORDER DATA, AND CORRESPONDING INTEGRATED CIRCUIT AND METHOD FOR MANAGING A BUFFER 有权
    用于订购不合规格数据的缓冲器，以及相关的集成电路和用于管理缓冲器的方法

    公开(公告)号：US20140185390A1

    公开(公告)日：2014-07-03

    申请号：US14143383

    申请日：2013-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Daniele Mangano ,  Salvatore Marco Rosselli ,  Giuseppe Falconeri

    IPC: G11C7/10

    CPC classification number: G11C7/1006 ,  G06F5/10 ,  G06F2205/106 ,  G06F2205/123

    Abstract: A buffer for ordering out-of-order data includes a memory with a plurality of memory locations for temporarily storing data and a detection circuit configured for generating a control signal when the memory locations contain valid data. The detection circuit includes a first block configured for generating validity signals that identify the memory locations containing valid data and a search circuit configured for determining a search pointer as a function of the validity signals. In the case where each memory location contains valid data, the search pointer indicates the last memory location. In the case where at least one memory location is still free, the search pointer indicates the first memory location that is free.

    Abstract translation: 用于排序无序数据的缓冲器包括具有用于临时存储数据的多个存储器位置的存储器和被配置为当存储器位置包含有效数据时生成控制信号的检测电路。 检测电路包括被配置用于产生识别包含有效数据的存储位置的有效信号的第一块和被配置为根据有效信号确定搜索指针的搜索电路。 在每个存储器位置包含有效数据的情况下，搜索指针指示最后的存储器位置。 在至少一个存储器位置仍然空闲的情况下，搜索指针指示第一存储器位置是空闲的。

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