公开(公告)号：US20240162329A1

公开(公告)日：2024-05-16

申请号：US18387325

申请日：2023-11-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexis GAUTHIER ,  Pascal CHEVALIER ,  Edoardo BREZZA ,  Nicolas GUITARD

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/737

Abstract: An electronic device includes an insulating first layer covering a second layer made of a doped semiconductor material. A cavity is formed to cross through the first layer and reach the second layer. Insulating spacers are forming against lateral walls of the cavity. A first doped semiconductor region fills the cavity. The first doped semiconductor region has a doping concentration decreasing from the second layer.

公开(公告)号：US20240162328A1

公开(公告)日：2024-05-16

申请号：US18387627

申请日：2023-11-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexis GAUTHIER ,  Pascal CHEVALIER ,  Edoardo BREZZA ,  Nicolas GUITARD ,  Gregory AVENIER

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/66234 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004

Abstract: A bipolar transistor is manufactured by: forming a collector region; forming a first layer made of a material of a base region and an insulating second layer; forming a cavity reaching the collector region; forming a portion of the collector region and a portion of the base region in the cavity; forming an insulating fourth layer made of a same material as the insulating second layer in the periphery of the bottom of the cavity, the insulating fourth layer having a same thickness as the insulating second layer; forming an emitter region; and simultaneously removing the insulating second and a portion of the insulating fourth layer not covered by the emitter region.

公开(公告)号：US20220122969A1

公开(公告)日：2022-04-21

申请号：US17503621

申请日：2021-10-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Edoardo BREZZA ,  Alexis GAUTHIER

IPC: H01L27/082 ,  H01L29/737 ,  H01L21/265 ,  H01L21/225 ,  H01L29/66 ,  H01L21/8222

Abstract: A bipolar transistor includes a collector region having a first doped portion located in a substrate and a second doped portion covering and in contact with an area of the first doped portion. The collector region has a doping profile having a peak in the first portion and a decrease from this peak up to in the second portion.

公开(公告)号：US20210273082A1

公开(公告)日：2021-09-02

申请号：US17175758

申请日：2021-02-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Edoardo BREZZA ,  A;exos GAUTHIER ,  Fabien DEPRAT ,  Pascal CHEVALIER

IPC: H01L29/737 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/66 ,  H01L29/417

Abstract: A method of making a bipolar transistor includes forming a stack of a first, second, third and fourth insulating layers on a substrate. An opening is formed in the stack to reach the substrate. An epitaxial process forms the collector of the transistor on the substrate and selectively etches an annular opening in the third layer. The intrinsic part of the base is then formed by epitaxy on the collector, with the intrinsic part being separated from the third layer by the annular opening. The junction between the collector and the intrinsic part of the base is surrounded by the second layer. The emitter is formed on the intrinsic part and the third layer is removed. A selective deposition of a semiconductor layer on the second layer and in direct contact with the intrinsic part forms the extrinsic part of the base.

公开(公告)号：US20230128033A1

公开(公告)日：2023-04-27

申请号：US17964350

申请日：2022-10-12

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Julien BORREL ,  Alexis GAUTHIER ,  Fanny HILARIO ,  Ludovic BERTHIER ,  Paul DUMAS ,  Edoardo BREZZA

IPC: H01L21/266 ,  H01L29/06

Abstract: According to one aspect provision is made of a method for ion implantation in a semiconductor wafer placed in an implantation chamber under vacuum, the semiconductor wafer having an integrated circuit area and a peripheral area around this integrated circuit area, the ion implantation allowing to apply a doping in regions, called implantation regions, of the integrated circuit area, the method comprising: forming a photosensitive resin coating serving as a mask on the semiconductor wafer, then forming openings in the photosensitive resin coating at said implantation regions of the integrated circuit area and at least at one region of the peripheral area, then implanting ions in the semiconductor wafer.

公开(公告)号：US20220059672A1

公开(公告)日：2022-02-24

申请号：US17401881

申请日：2021-08-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexis GAUTHIER ,  Edoardo BREZZA ,  Pascal CHEVALIER

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/08 ,  H01L29/732

Abstract: A bipolar transistor includes a stack of an emitter, a base, and a collector. The base is structured to have a comb shape including fingers oriented in a plane orthogonal to a stacking direction of the stack.