公开(公告)号：US09748955B1

公开(公告)日：2017-08-29

申请号：US15363041

申请日：2016-11-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Gilles Gasiot ,  Victor Malherbe ,  Sylvain Clerc

IPC: H03K19/00 ,  H03K19/003 ,  H03K19/21 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H03K19/00338 ,  H01L21/823892 ,  H01L27/0266 ,  H01L27/092 ,  H01L27/0928 ,  H03K19/21

Abstract: A radiation-hardened logic device includes a first n-channel transistor coupled by its main conducting nodes between an output node of a logic device and a supply voltage rail and a first p-channel transistor coupled by its main conducting nodes between the output node of the logic device and a ground voltage rail. The gates of the first n-channel and p-channel transistors are coupled to the output node.

公开(公告)号：US11730433B2

公开(公告)日：2023-08-22

申请号：US17529543

申请日：2021-11-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Gilles Gasiot ,  Severin Trochut ,  Olivier Le Neel ,  Victor Malherbe

IPC: A61B6/00 ,  G01T1/24

CPC classification number: A61B6/4208 ,  G01T1/24

Abstract: An X-ray detector includes a first circuit with an NPN-type bipolar transistor and a second circuit configured to compare a voltage at a terminal of the NPN-type bipolar transistor with a reference value substantially equal to a value of the terminal voltage which would occur when the first circuit has been exposed to a threshold quantity of X-rays.

公开(公告)号：US10771048B2

公开(公告)日：2020-09-08

申请号：US16747341

申请日：2020-01-20

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Capucine Lecat-Mathieu De Boissac ,  Fady Abouzeid ,  Gilles Gasiot ,  Philippe Roche ,  Victor Malherbe

IPC: H03K5/14 ,  H03K5/135 ,  H03K5/00

Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.