公开(公告)号：US20190244857A1

公开(公告)日：2019-08-08

申请号：US16384147

申请日：2019-04-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Didier DUTARTRE ,  Jean-Pierre CARRERE ,  Jean-Luc HUGUENIN ,  Clement PRIBAT ,  Sarah KUSTER

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/74 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/76877 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/743 ,  H01L21/7624 ,  H01L21/823475 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/0649

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

公开(公告)号：US20240274552A1

公开(公告)日：2024-08-15

申请号：US18625631

申请日：2024-04-03

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier DUTARTRE

IPC: H01L23/66 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L23/66 ,  H01L21/76286 ,  H01L29/0646 ,  H01L29/0649 ,  H01L2223/6688

Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.

公开(公告)号：US20210376170A1

公开(公告)日：2021-12-02

申请号：US17324619

申请日：2021-05-19

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier DUTARTRE

IPC: H01L31/028 ,  G01S7/4865 ,  H01L27/146 ,  H01L31/103

Abstract: An integrated optical sensor is formed by a pinned photodiode. A semiconductor substrate includes a first semiconductor region having a first type of conductivity located between a second semiconductor region having a second type of conductivity opposite to the first type one and a third semiconductor region having the second type of conductivity. The third semiconductor region is thicker, less doped and located deeper in the substrate than the second semiconductor region. The third semiconductor region includes both silicon and germanium. In one implementation, the germanium within the third semiconductor region has at least one concentration gradient. In another implementation, the germanium concentration within the third semiconductor region is substantially constant.

公开(公告)号：US20190131521A1

公开(公告)日：2019-05-02

申请号：US16168369

申请日：2018-10-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pierre MORIN ,  Didier DUTARTRE

IPC: H01L45/00

Abstract: A memory cell includes a phase-change material. A via is connected to a transistor and an element for heating the phase-change material. A layer made of a material (which is one of electrically insulating or has an electric resistivity greater than 2.5·10−5 Ω·m and which is sufficiently thin to be crossable by an electric current due to a tunnel-type effect) is positioned between the via and the heating element. Interfaces between the layer and materials in contact with surfaces of said layer form a thermal barrier.

公开(公告)号：US20180374983A1

公开(公告)日：2018-12-27

申请号：US16008613

申请日：2018-06-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Dominique GOLANSKI ,  Jean JIMENEZ ,  Didier DUTARTRE ,  Olivier GONNARD

IPC: H01L31/18 ,  H01L31/107 ,  H01L29/66 ,  H01L21/265

Abstract: A method for manufacturing a SPAD photodiode starts with the delimitation of a formation area for the SPAD photodiode in a layer of semiconductor material that is doped with a first dopant type. Dopant of a second dopant type is implanted in the layer of semiconductor material to form a buried region within the formation area. An epitaxial layer is then grown on the layer of semiconductor material at least over the formation area. MOS transistors are then formed on and in the epitaxial layer at locations outside of the formation area.

公开(公告)号：US20220352028A1

公开(公告)日：2022-11-03

申请号：US17729191

申请日：2022-04-26

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierpaolo MONGE ROFFARELLO ,  Isabella MICA ,  Didier DUTARTRE ,  Alexandra ABBADIE

IPC: H01L21/8249 ,  H01L27/06 ,  H01L21/02 ,  H01L21/324 ,  H01L21/763

Abstract: A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.

公开(公告)号：US20190131520A1

公开(公告)日：2019-05-02

申请号：US16168131

申请日：2018-10-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pierre MORIN ,  Franck ARNAUD ,  Didier DUTARTRE

IPC: H01L45/00

Abstract: A memory cell includes a phase-change material. A via is electrically connected with a transistor and an element for heating the phase-change material. An electrically-conductive thermal barrier is positioned between the via and the heating element.

公开(公告)号：US20230197868A1

公开(公告)日：2023-06-22

申请号：US18109955

申请日：2023-02-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier DUTARTRE

IPC: H01L31/0312 ,  H01L31/107

CPC classification number: H01L31/03125 ,  H01L31/107 ,  G06F1/1605

Abstract: An integrated optical sensor includes a photon-detection module of a single-photon avalanche photodiode type. The detection module includes a semiconductive active zone in a substrate. The semiconductive active zone includes a region that contains germanium with a percentage between 3% and 10%. This percentage range is advantageous because it makes it possible to obtain a material firstly containing germanium (which in particular increases the efficiency of the sensor in the infrared or near infrared domain) and secondly having no or very few dislocations (which facilitates the implementation of a functional sensor in integrated form).

公开(公告)号：US20190267335A1

公开(公告)日：2019-08-29

申请号：US16278313

申请日：2019-02-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier DUTARTRE

IPC: H01L23/66 ,  H01L29/06 ,  H01L21/762

Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.

公开(公告)号：US20250126877A1

公开(公告)日：2025-04-17

申请号：US18986599

申请日：2024-12-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierpaolo MONGE ROFFARELLO ,  Isabella MICA ,  Didier DUTARTRE ,  Alexandra ABBADIE

IPC: H10D84/03 ,  H01L21/02 ,  H01L21/324 ,  H01L21/763 ,  H10D84/01 ,  H10D84/40

Abstract: A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.