公开(公告)号：US20190131521A1

公开(公告)日：2019-05-02

申请号：US16168369

申请日：2018-10-23

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Pierre MORIN ,  Didier DUTARTRE

IPC分类号： H01L45/00

摘要： A memory cell includes a phase-change material. A via is connected to a transistor and an element for heating the phase-change material. A layer made of a material (which is one of electrically insulating or has an electric resistivity greater than 2.5·10−5 Ω·m and which is sufficiently thin to be crossable by an electric current due to a tunnel-type effect) is positioned between the via and the heating element. Interfaces between the layer and materials in contact with surfaces of said layer form a thermal barrier.

公开(公告)号：US20180323237A1

公开(公告)日：2018-11-08

申请号：US15968474

申请日：2018-05-01

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Pierre MORIN ,  Philippe BRUN ,  Laurent-Luc CHAPELON

IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02

CPC分类号： H01L27/2463 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

摘要： A phase-change memory includes a strip of phase-change material that is coated with a conductive strip and surrounded by an insulator. The strip of phase-change material has a lower face in contact with tips of a resistive element. A connection network composed of several levels of metallization coupled with one another by conducting vias is provided above the conductive strip. At least one element of a lower level of the metallization is in direct contact with the upper surface of the conductive strip.

公开(公告)号：US20180301625A1

公开(公告)日：2018-10-18

申请号：US15953921

申请日：2018-04-16

申请人： STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics S.r.l.

发明人： Pierre MORIN ,  Michel HAOND ,  Paola ZULIANI

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/126 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608

摘要： A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.

公开(公告)号：US20230263082A1

公开(公告)日：2023-08-17

申请号：US18130184

申请日：2023-04-03

申请人： STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

发明人： Franck ARNAUD ,  David GALPIN ,  Stephane ZOLL ,  Olivier HINSINGER ,  Laurent FAVENNEC ,  Jean-Pierre ODDOU ,  Lucile BROUSSOUS ,  Philippe BOIVIN ,  Olivier WEBER ,  Philippe BRUN ,  Pierre MORIN

IPC分类号： H10N70/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC分类号： H10N70/8616 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/882 ,  H10N70/8265 ,  H10N70/8413 ,  G11C2013/008

摘要： An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

公开(公告)号：US20190140176A1

公开(公告)日：2019-05-09

申请号：US16184246

申请日：2018-11-08

申请人： STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

发明人： Franck ARNAUD ,  David GALPIN ,  Stephane ZOLL ,  Olivier HINSINGER ,  Laurent FAVENNEC ,  Jean-Pierre ODDOU ,  Lucile BROUSSOUS ,  Philippe BOIVIN ,  Olivier WEBER ,  Philippe BRUN ,  Pierre MORIN

IPC分类号： H01L45/00 ,  H01L27/24

摘要： An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

公开(公告)号：US20190131520A1

公开(公告)日：2019-05-02

申请号：US16168131

申请日：2018-10-23

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Pierre MORIN ,  Franck ARNAUD ,  Didier DUTARTRE

IPC分类号： H01L45/00

摘要： A memory cell includes a phase-change material. A via is electrically connected with a transistor and an element for heating the phase-change material. An electrically-conductive thermal barrier is positioned between the via and the heating element.