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1.发明申请公开(公告)号：US20160170467A1
公开(公告)日：2016-06-16
申请号：US14852513
申请日：2015-09-12
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jonathan Cottinet , Jean Claude Bini
CPC classification number: G06F1/324 , G06F1/3287 , G06F3/167 , G10L15/22 , G10L15/28 , G10L2015/088 , H04W52/0229 , H04W52/0251 , H04W52/0293 , H04W76/28 , Y02D70/00 , Y02D70/26
Abstract: An electronic device includes an appended module coupled to a core having a standby state comprising a first power supply circuit, a first clock and a circuit that recognizes multiple vocal commands timed by the first clock. The appended module includes a second power supply circuit independent of the first power supply circuit, a second clock independent of the first clock and having a frequency lower than that of the first clock, digital unit timed by the second clock including a sound capture circuit that delivers a processed sound signal, and a processing unit configured in order, in the presence of a parameter of the processed sound signal greater than a threshold, to analyze the content of the processed sound signal and to deliver, when the content of the sound signal comprises a reference pattern, an activating signal to the core that can take it out of its standby state.
Abstract translation: 电子设备包括耦合到具有备用状态的核心的附加模块，其包括第一电源电路，第一时钟和识别由第一时钟定时的多个声控命令的电路。 附加的模块包括独立于第一电源电路的第二电源电路，独立于第一时钟并且具有低于第一时钟的频率的第二时钟，由第二时钟定时的数字单元包括声音捕获电路， 传送经处理的声音信号，以及处理单元，在存在大于阈值的处理声音信号的参数的情况下，依次配置，以分析处理后的声音信号的内容，并且当声音信号的内容 包括参考图案，到芯的激活信号，其可以使其退出其待机状态。
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公开(公告)号：US20230161646A1
公开(公告)日：2023-05-25
申请号：US18058648
申请日：2022-11-23
Inventor： Isabelle Carnel , Valerie Assemat , Edwin Hilkens , Jeremy Ribeiro De Freitas , Jean Claude Bini
CPC classification number: G06F9/542 , G06F9/4881
Abstract: In an embodiment an integrated circuit includes a digital-signal processing unit having an event management device configured to associate respective event data items with respective trigger signals and a digital-signal processor configured to associate a respective task with an respective event data item, wherein the event management device is configured to receive the trigger signals at input terminals and, when a trigger signal is received, store the event data item associated with the received trigger signal in an event register, and wherein the digital-signal processor is configured execute the task associated with the event data item stored in the event register.
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公开(公告)号：US10955898B2
公开(公告)日：2021-03-23
申请号：US15989731
申请日：2018-05-25
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jonathan Cottinet , Jean Claude Bini
Abstract: An electronic device includes an appended module coupled to a core having a standby state comprising a first power supply circuit, a first clock and a circuit that recognizes multiple vocal commands timed by the first clock. The appended module includes a second power supply circuit independent of the first power supply circuit, a second clock independent of the first clock and having a frequency lower than that of the first clock, digital unit timed by the second clock including a sound capture circuit that delivers a processed sound signal, and a processing unit configured in order, in the presence of a parameter of the processed sound signal greater than a threshold, to analyze the content of the processed sound signal and to deliver, when the content of the sound signal comprises a reference pattern, an activating signal to the core that can take it out of its standby state.
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公开(公告)号：US10593361B2
公开(公告)日：2020-03-17
申请号：US15867223
申请日：2018-01-10
Inventor： Jonathan Cottinet , Jean Claude Bini
Abstract: A method for transmitting and/or receiving a potential aggressor audio signal includes a transmission and/or a reception of successive groups of data timed by a first clock signal within respective successive frames synchronized by a second clock signal. In the presence of a risk of interference of the potential aggressor audio signal with a different, potential victim, signal, during the transmission or reception of the potential aggressor audio signal, the frequency of the first clock signal is modified while keeping the frequency of the second clock signal unchanged.
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公开(公告)号：US10001829B2
公开(公告)日：2018-06-19
申请号：US14852513
申请日：2015-09-12
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jonathan Cottinet , Jean Claude Bini
CPC classification number: G06F1/324 , G06F1/3287 , G06F3/167 , G10L15/22 , G10L15/28 , G10L2015/088 , H04W52/0229 , H04W52/0251 , H04W52/0293 , H04W76/28 , Y02D70/00 , Y02D70/26
Abstract: An electronic device includes an appended module coupled to a core having a standby state comprising a first power supply circuit, a first clock and a circuit that recognizes multiple vocal commands timed by the first clock. The appended module includes a second power supply circuit independent of the first power supply circuit, a second clock independent of the first clock and having a frequency lower than that of the first clock, digital unit timed by the second clock including a sound capture circuit that delivers a processed sound signal, and a processing unit configured in order, in the presence of a parameter of the processed sound signal greater than a threshold, to analyze the content of the processed sound signal and to deliver, when the content of the sound signal comprises a reference pattern, an activating signal to the core that can take it out of its standby state.
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Patent Agency Ranking
公开(公告)号：US20180275737A1
公开(公告)日：2018-09-27
申请号：US15989731
申请日：2018-05-25
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jonathan Cottinet , Jean Claude Bini
CPC classification number: G06F1/324 , G06F1/3287 , G06F3/167 , G10L15/22 , G10L15/28 , G10L2015/088 , H04W52/0229 , H04W52/0251 , H04W52/0293 , H04W76/28 , Y02D70/00 , Y02D70/26
Abstract: An electronic device includes an appended module coupled to a core having a standby state comprising a first power supply circuit, a first clock and a circuit that recognizes multiple vocal commands timed by the first clock. The appended module includes a second power supply circuit independent of the first power supply circuit, a second clock independent of the first clock and having a frequency lower than that of the first clock, digital unit timed by the second clock including a sound capture circuit that delivers a processed sound signal, and a processing unit configured in order, in the presence of a parameter of the processed sound signal greater than a threshold, to analyze the content of the processed sound signal and to deliver, when the content of the sound signal comprises a reference pattern, an activating signal to the core that can take it out of its standby state.
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公开(公告)号：US20180130492A1
公开(公告)日：2018-05-10
申请号：US15867223
申请日：2018-01-10
Inventor： Jonathan Cottinet , Jean Claude Bini
CPC classification number: G11B20/10222 , G06F3/165 , H04B15/04 , H04B2215/065 , H04L7/04
Abstract: A method for transmitting and/or receiving a potential aggressor audio signal includes a transmission and/or a reception of successive groups of data timed by a first clock signal within respective successive frames synchronized by a second clock signal. In the presence of a risk of interference of the potential aggressor audio signal with a different, potential victim, signal, during the transmission or reception of the potential aggressor audio signal, the frequency of the first clock signal is modified while keeping the frequency of the second clock signal unchanged.
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8.发明申请公开(公告)号：US20180063638A1
公开(公告)日：2018-03-01
申请号：US15473812
申请日：2017-03-30
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics Design and Application S.R.O. , STMicroelectronics (Alps) SAS
Inventor： Jean Claude Bini , Dragos Davidescu , Igor Cesko , Jonathan Cottinet
CPC classification number: H04R3/005 , G10K11/346 , H04R1/406 , H04R3/04 , H04R19/005 , H04R2201/003 , H04R2430/23
Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.
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公开(公告)号：US10264353B2
公开(公告)日：2019-04-16
申请号：US15473812
申请日：2017-03-30
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics Design and Application S.R.O. , STMicroelectronics (Alps) SAS
Inventor： Jean Claude Bini , Dragos Davidescu , Igor Cesko , Jonathan Cottinet
Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.
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公开(公告)号：US09905262B2
公开(公告)日：2018-02-27
申请号：US14918614
申请日：2015-10-21
Inventor： Jonathan Cottinet , Jean Claude Bini
CPC classification number: G11B20/10222 , G06F3/165 , H04B15/04 , H04B2215/065 , H04L7/04
Abstract: A method for transmitting and/or receiving a potential aggressor audio signal includes a transmission and/or a reception of successive groups of data timed by a first clock signal within respective successive frames synchronized by a second clock signal. In the presence of a risk of interference of the potential aggressor audio signal with a different, potential victim, signal, during the transmission or reception of the potential aggressor audio signal, the frequency of the first clock signal is modified while keeping the frequency of the second clock signal unchanged.
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