公开(公告)号：US20210158887A1

公开(公告)日：2021-05-27

申请号：US17096090

申请日：2020-11-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christophe Eva ,  Jean-Michel Gril-Maffre

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/10

Abstract: An embodiment method for writing to a volatile memory comprises at least receiving a request to write to the memory, and, in response to each request to write to the memory: preparation of data to be written to the memory, this comprising computing an error correction code; storing in a buffer register the data to be written to the memory; and, if no new request to write to or to read from the memory is received after the storage, writing to the memory of the data to be written stored in the buffer register.

公开(公告)号：US11550377B2

公开(公告)日：2023-01-10

申请号：US17396070

申请日：2021-08-06

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Herve Cassagnes ,  Cyril Moulin ,  Jean-Michel Gril-Maffre

IPC: H03K3/00 ,  G06F1/24 ,  H03K17/22 ,  H03K19/17736 ,  H03K3/012

Abstract: Integrated circuit, method for resetting and computer program product. The integrated circuit comprises a first portion and a second portion. The first portion comprises a reset input configured to receive a reset signal, an activation module connected to the reset input. The activation module is configured to activate the second portion upon reception of the reset signal. The first portion comprises an emissions module configured to emit a replicated reset signal. The second portion can be selectively activated or deactivated. The second portion comprises a reset input configured to receive the replicated reset signal of the emissions module, a determination module configured to determine that an elapsed time starting from the activation of the second portion of the circuit oversteps a threshold.

公开(公告)号：US11189360B2

公开(公告)日：2021-11-30

申请号：US16669184

申请日：2019-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Jean-Michel Gril-Maffre ,  Christophe Eva

IPC: G11C29/00 ,  G06F11/10 ,  G06F12/06

Abstract: A system includes a memory device that includes a first memory region to store first data at first addresses, and a second memory region to store, on command, either second data at second addresses or error correction code check bits associated with the first data at third addresses.

公开(公告)号：US11120887B2

公开(公告)日：2021-09-14

申请号：US17096090

申请日：2020-11-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christophe Eva ,  Jean-Michel Gril-Maffre

IPC: G11C29/42 ,  G11C7/10 ,  G11C29/44

Abstract: An embodiment method for writing to a volatile memory comprises at least receiving a request to write to the memory, and, in response to each request to write to the memory: preparation of data to be written to the memory, this comprising computing an error correction code; storing in a buffer register the data to be written to the memory; and, if no new request to write to or to read from the memory is received after the storage, writing to the memory of the data to be written stored in the buffer register.

公开(公告)号：US20180329721A1

公开(公告)日：2018-11-15

申请号：US16026233

申请日：2018-07-03

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Froidevaux ,  Jean-Michel Gril-Maffre ,  Jean-Pierre Leca

IPC: G06F9/4401 ,  H03K19/00 ,  G06F1/24 ,  G06F1/32 ,  G06F1/28

Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.

公开(公告)号：US11495275B2

公开(公告)日：2022-11-08

申请号：US17336841

申请日：2021-06-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christophe Eva ,  Jean-Michel Gril-Maffre

IPC: G11C7/22 ,  G06F13/42 ,  G11C7/10 ,  G11C16/34

Abstract: A random access memory is connected to a processing unit through a memory interface. Access to the random access is memory is controlled by a process. The memory interface receives a request for access to the memory issued by the processing unit. In response to the request, the memory interface indicates to the processing unit that the memory is not available to receive another access request during a duration of unavailability. This duration can be differentiated depending on whether the received request is a write or read request. The value of the duration of unavailability associated with a write request and the value of the duration of unavailability associated with a read request are individually programmable independently of each other.

公开(公告)号：US10719331B2

公开(公告)日：2020-07-21

申请号：US16026233

申请日：2018-07-03

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Froidevaux ,  Jean-Michel Gril-Maffre ,  Jean-Pierre Leca

IPC: G06F1/24 ,  G06F9/4401 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3296 ,  H03K19/00

Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.

公开(公告)号：US20170147362A1

公开(公告)日：2017-05-25

申请号：US15153118

申请日：2016-05-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Froidevaux ,  Jean-Michel Gril-Maffre ,  Jean-Pierre Leca

IPC: G06F9/44 ,  G06F1/28 ,  G06F1/32 ,  H03K19/00

CPC classification number: G06F9/4418 ,  G06F1/24 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3296 ,  G06F9/4403 ,  G06F9/442 ,  H03K19/0016

Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.

公开(公告)号：US20200174927A1

公开(公告)日：2020-06-04

申请号：US16669184

申请日：2019-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Jean-Michel Gril-Maffre ,  Christophe Eva

IPC: G06F12/06 ,  G06F11/10

Abstract: A system includes a memory device that includes a first memory region to store first data at first addresses, and a second memory region to store, on command, either second data at second addresses or error correction code check bits associated with the first data at third addresses.