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公开(公告)号:US11133798B2
公开(公告)日:2021-09-28
申请号:US16856448
申请日:2020-04-23
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Nicolas Froidevaux , Laurent Lopez
IPC: H03K17/687 , H03K17/30
Abstract: A device includes a first connection pin, a second connection pin, a third connection pin, and a fourth connection pin. The second connection pin is configured to be connected to a supply voltage. The fourth connection pin is configured to be coupled to a reference voltage. The device further includes a first transistor including: a first gate and a first source/drain coupled to the first connection pin; a second transistor including a second gate and a second source/drain connected to the first transistor; and a third transistor including a third gate, a third source/drain connected to the second transistor, and a fourth source/drain connected to the fourth connection pin. The third transistor is configured to be controlled by a digital signal using the third connection pin. Both the first gate and the second gate are directly connected to the second connection pin.
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公开(公告)号:US11680835B2
公开(公告)日:2023-06-20
申请号:US17155880
申请日:2021-01-22
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Nicolas Froidevaux , Laurent Lopez
Abstract: An oscillating analog signal includes a succession of dampened oscillations. That oscillating analog signal is conditioned to generate an output signal including only oscillations of the oscillating analog signal which have an amplitude smaller than a first threshold. The output signal is then processed by a processing unit, where the first threshold is compatible with a maximum level of voltage tolerable by the processing unit.
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公开(公告)号:US20210384903A1
公开(公告)日:2021-12-09
申请号:US17411838
申请日:2021-08-25
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Nicolas Froidevaux , Laurent Lopez
IPC: H03K17/687 , H03K17/30
Abstract: An electronic chip includes a chip core including an input terminal, an output terminal, an external pad, and an input-output circuit coupled to the chip core and the external pad. The input-output circuit includes an enable terminal coupled to the chip core, a connection terminal coupled to the external pad, a switchable diode device coupled between a supply voltage and a reference voltage, and a levelling circuit. The switchable diode device is coupled to the connection terminal and the enable terminal and is configured to operate as a diode in response to a control signal in a first state applied to the enable terminal and to operate as an open circuit in response to the control signal in a second state applied to the enable terminal. The levelling circuit is coupled to the connection terminal, the input terminal of the chip core, and the output terminal of the chip core.
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公开(公告)号:US20180329721A1
公开(公告)日:2018-11-15
申请号:US16026233
申请日:2018-07-03
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Nicolas Froidevaux , Jean-Michel Gril-Maffre , Jean-Pierre Leca
IPC: G06F9/4401 , H03K19/00 , G06F1/24 , G06F1/32 , G06F1/28
Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.
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公开(公告)号:US11509305B2
公开(公告)日:2022-11-22
申请号:US17411838
申请日:2021-08-25
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Nicolas Froidevaux , Laurent Lopez
IPC: H03K17/687 , H03K17/30
Abstract: An electronic chip includes a chip core including an input terminal, an output terminal, an external pad, and an input-output circuit coupled to the chip core and the external pad. The input-output circuit includes an enable terminal coupled to the chip core, a connection terminal coupled to the external pad, a switchable diode device coupled between a supply voltage and a reference voltage, and a levelling circuit. The switchable diode device is coupled to the connection terminal and the enable terminal and is configured to operate as a diode in response to a control signal in a first state applied to the enable terminal and to operate as an open circuit in response to the control signal in a second state applied to the enable terminal. The levelling circuit is coupled to the connection terminal, the input terminal of the chip core, and the output terminal of the chip core.
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公开(公告)号:US10217717B2
公开(公告)日:2019-02-26
申请号:US15137144
申请日:2016-04-25
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Nicolas Froidevaux , Yann Bacher
IPC: H01L23/00 , H01L23/50 , H01L23/528 , H01L23/31
Abstract: An integrated circuit includes peripheral conductive pads interconnected by a peripheral conductive track within an integrated circuit chip. The integrated circuit chip further includes internal conductive pads interconnected by an internal conductive track within the integrated circuit chip. A conductive bonding wire external to the integrated circuit chip connects the one peripheral conductive pad to one internal conductive pad. A package encapsulates the integrated circuit chip and the conductive bonding wire.
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公开(公告)号:US09638728B2
公开(公告)日:2017-05-02
申请号:US14947858
申请日:2015-11-20
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Yann Bacher , Nicolas Froidevaux
IPC: G01R19/165 , H02M3/04 , G01R19/25
CPC classification number: G01R19/16585 , G01R19/2503 , H02M3/04
Abstract: A circuit has a supply line, a reference line and circuitry coupled between the supply line and the reference line. The circuitry outputs a regulated voltage and a measurement voltage. An analog-to-digital converter (ADC) generates a digital signal indicative of variations of potential differences between the supply line and the reference line based on the regulated voltage and the measurement voltage. The generated digital signal may be used to control the circuit.
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公开(公告)号:US20200343890A1
公开(公告)日:2020-10-29
申请号:US16856448
申请日:2020-04-23
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Nicolas Froidevaux , Laurent Lopez
IPC: H03K17/687
Abstract: A device comprising transistors in a series connection is disclosed. In an embodiment a device includes a first transistor, a second transistor connected to the first transistor and a third transistor connected to the second transistor, wherein the transistors are connected in a series connection, and wherein the third transistor is configured to be controlled by a digital signal.
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公开(公告)号:US10719331B2
公开(公告)日:2020-07-21
申请号:US16026233
申请日:2018-07-03
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Nicolas Froidevaux , Jean-Michel Gril-Maffre , Jean-Pierre Leca
IPC: G06F1/24 , G06F9/4401 , G06F1/28 , G06F1/32 , G06F1/3203 , G06F1/3296 , H03K19/00
Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.
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公开(公告)号:US20170147362A1
公开(公告)日:2017-05-25
申请号:US15153118
申请日:2016-05-12
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Nicolas Froidevaux , Jean-Michel Gril-Maffre , Jean-Pierre Leca
CPC classification number: G06F9/4418 , G06F1/24 , G06F1/28 , G06F1/32 , G06F1/3203 , G06F1/3296 , G06F9/4403 , G06F9/442 , H03K19/0016
Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.
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