公开(公告)号：US20130229875A1

公开(公告)日：2013-09-05

申请号：US13786202

申请日：2013-03-05

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Francesco La Rosa ,  Olivier Pizzuto ,  Stephan Niel ,  Philippe Boivin ,  Pascal Fornara ,  Laurent Lopez ,  Arnaud Regnier

IPC: G11C16/26 ,  G11C16/14

CPC classification number: G11C16/26 ,  G11C8/12 ,  G11C11/5642 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/7881

Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.

Abstract translation: 本公开涉及一种读取和写入存储单元的方法，每个存储单元包括与选择晶体管串联的电荷累积晶体管，包括将选择电压施加到存储器单元的选择晶体管的栅极; 将读取电压施加到存储单元的电荷累积晶体管的控制栅极; 将选择电压施加到耦合到相同位线的第二存储器单元的选择晶体管的栅极; 以及向第二存储单元的电荷累积晶体管的控制栅极施加抑制电压，以保持晶体管处于阻塞状态。

公开(公告)号：US08830761B2

公开(公告)日：2014-09-09

申请号：US13786202

申请日：2013-03-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Olivier Pizzuto ,  Stephan Niel ,  Philippe Boivin ,  Pascal Fornara ,  Laurent Lopez ,  Arnaud Regnier

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/34 ,  G11C16/14 ,  G11C16/08 ,  H01L29/423 ,  H01L29/788 ,  H01L27/115 ,  G11C16/04 ,  G11C11/56 ,  G11C8/12

CPC classification number: G11C16/26 ,  G11C8/12 ,  G11C11/5642 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/7881

Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.

Abstract translation: 本公开涉及一种读取和写入存储单元的方法，每个存储单元包括与选择晶体管串联的电荷累积晶体管，包括将选择电压施加到存储器单元的选择晶体管的栅极; 将读取电压施加到存储单元的电荷累积晶体管的控制栅极; 将选择电压施加到耦合到相同位线的第二存储器单元的选择晶体管的栅极; 以及向第二存储单元的电荷累积晶体管的控制栅极施加抑制电压，以保持晶体管处于阻塞状态。