公开(公告)号：US12232435B2

公开(公告)日：2025-02-18

申请号：US18130184

申请日：2023-04-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

公开(公告)号：US11800821B2

公开(公告)日：2023-10-24

申请号：US17856711

申请日：2022-07-01

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Daniel Benoit ,  Remy Berthelon

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10B63/30 ,  H10N70/021 ,  H10N70/826

Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.

公开(公告)号：US11411177B2

公开(公告)日：2022-08-09

申请号：US16879577

申请日：2020-05-20

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Daniel Benoit ,  Remy Berthelon

IPC: H01L29/02 ,  H01L45/00 ,  H01L27/24

Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.

公开(公告)号：US11031550B2

公开(公告)日：2021-06-08

申请号：US16457855

申请日：2019-06-28

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Simon Jeannot

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

公开(公告)号：US10319906B2

公开(公告)日：2019-06-11

申请号：US15352985

申请日：2016-11-16

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin

IPC: H01L27/24 ,  H01L45/00

Abstract: A oxide-based direct-access resistive nonvolatile memory may include within the interconnect portion of the integrated circuit a memory plane including capacitive memory cells extending in orthogonal first and second directions and each including a first electrode, a dielectric region and a second electrode. The memory plane may include conductive pads of square or rectangular shape forming the first electrodes. The stack of the dielectric layer and the second conductive layer covers the pads in the first direction and forms, in the second direction, conductive bands extending over and between the pads. The second electrodes may be formed by zones of the second bands facing the pads.

公开(公告)号：US09929146B2

公开(公告)日：2018-03-27

申请号：US15454788

申请日：2017-03-09

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Olivier Weber ,  Emmanuel Richard ,  Philippe Boivin

IPC: H01L27/06 ,  H01L29/732 ,  H01L21/84 ,  H01L21/8249 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1207 ,  H01L27/2445 ,  H01L29/0813 ,  H01L29/41708 ,  H01L29/66303 ,  H01L29/732 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.

公开(公告)号：US09559297B2

公开(公告)日：2017-01-31

申请号：US15214054

申请日：2016-07-19

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Julien Delalleau

IPC: H01L43/12 ,  H01L27/24 ,  H01L27/115 ,  H01L27/22 ,  H01L29/423 ,  H01L29/78 ,  H01L45/00 ,  H01L43/02 ,  H01L43/08 ,  H01L21/265 ,  H01L21/762

CPC classification number: H01L43/12 ,  H01L21/26513 ,  H01L21/76224 ,  H01L23/528 ,  H01L27/11507 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L29/42356 ,  H01L29/7827 ,  H01L43/02 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method of making a memory on semiconductor substrate, comprising: at least one data line, at least one selection line, at least one reference line, at least one memory cell comprising a select transistor having a control gate connected to the selection line, a first conduction terminal connected to a variable impedance element, the select transistor and the variable impedance element coupling the reference line to the data line, the select transistor comprising an embedded vertical gate produced in a trench formed in the substrate, and a channel region opposite a first face of the trench, between a first deep doped region and a second doped region on the surface of the substrate coupled to the variable impedance element.

Abstract translation: 本公开涉及一种在半导体衬底上制造存储器的方法，包括：至少一条数据线，至少一条选择线，至少一条参考线，至少一个存储单元，包括选择晶体管，其具有连接到 所述选择线，连接到可变阻抗元件的第一导电端子，所述选择晶体管和所述参考线耦合到所述数据线的所述可变阻抗元件，所述选择晶体管包括在形成在所述衬底中的沟槽中产生的嵌入垂直栅极，以及 与沟槽的第一面相对的沟道区，位于耦合到可变阻抗元件的衬底表面上的第一深掺杂区和第二掺杂区之间。

公开(公告)号：US20160380030A1

公开(公告)日：2016-12-29

申请号：US14970347

申请日：2015-12-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Simon Jeannot

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G11C13/0004 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1666

Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

Abstract translation: 本公开涉及一种形成在晶片中的存储单元，其包括被第一绝缘层覆盖的半导体衬底，绝缘层被由半导体制成的有源层覆盖，所述存储单元包括具有控制栅极和第一绝缘层的选择晶体管 所述导电端子连接到可变电阻元件，所述栅极形成在所述有源层上并具有被第二绝缘层覆盖的侧面，所述可变电阻元件由可变电阻材料层形成，所述可变电阻材料层沉积在侧向 有源层的沿着栅极的侧面通过有源层形成的第一沟槽的侧面，沟槽导体形成在第一沟槽中，抵抗可变电阻材料层的侧面。

公开(公告)号：US20160079391A1

公开(公告)日：2016-03-17

申请号：US14946408

申请日：2015-11-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/225 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66666 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/2253 ,  H01L21/2257 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/10876 ,  H01L27/2454 ,  H01L29/0676 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

Abstract: The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.

Abstract translation: 本发明涉及一种制造垂直MOS晶体管的方法，包括以下步骤：在半导体表面之上形成至少一个电介质层中的导电层; 通过至少导电层蚀刻孔，所述孔暴露所述导电层的内侧边缘和所述半导体表面的一部分; 在导电层的内侧边缘上形成栅极氧化物，在半导体表面的部分上形成底部氧化物; 在所述孔的侧边缘上形成蚀刻保护侧壁，所述侧壁覆盖所述栅极氧化物和所述底部氧化物的外部区域，留下所述底部氧化物的内部区域; 蚀刻底部氧化物的暴露的内部区域，直到达到半导体表面; 以及在所述孔中沉积半导体材料。

公开(公告)号：US20130229875A1

公开(公告)日：2013-09-05

申请号：US13786202

申请日：2013-03-05

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Francesco La Rosa ,  Olivier Pizzuto ,  Stephan Niel ,  Philippe Boivin ,  Pascal Fornara ,  Laurent Lopez ,  Arnaud Regnier

IPC: G11C16/26 ,  G11C16/14

CPC classification number: G11C16/26 ,  G11C8/12 ,  G11C11/5642 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/7881

Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.

Abstract translation: 本公开涉及一种读取和写入存储单元的方法，每个存储单元包括与选择晶体管串联的电荷累积晶体管，包括将选择电压施加到存储器单元的选择晶体管的栅极; 将读取电压施加到存储单元的电荷累积晶体管的控制栅极; 将选择电压施加到耦合到相同位线的第二存储器单元的选择晶体管的栅极; 以及向第二存储单元的电荷累积晶体管的控制栅极施加抑制电压，以保持晶体管处于阻塞状态。