公开(公告)号：US20200343890A1

公开(公告)日：2020-10-29

申请号：US16856448

申请日：2020-04-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Froidevaux ,  Laurent Lopez

IPC: H03K17/687

Abstract: A device comprising transistors in a series connection is disclosed. In an embodiment a device includes a first transistor, a second transistor connected to the first transistor and a third transistor connected to the second transistor, wherein the transistors are connected in a series connection, and wherein the third transistor is configured to be controlled by a digital signal.

公开(公告)号：US20210384903A1

公开(公告)日：2021-12-09

申请号：US17411838

申请日：2021-08-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Froidevaux ,  Laurent Lopez

IPC: H03K17/687 ,  H03K17/30

Abstract: An electronic chip includes a chip core including an input terminal, an output terminal, an external pad, and an input-output circuit coupled to the chip core and the external pad. The input-output circuit includes an enable terminal coupled to the chip core, a connection terminal coupled to the external pad, a switchable diode device coupled between a supply voltage and a reference voltage, and a levelling circuit. The switchable diode device is coupled to the connection terminal and the enable terminal and is configured to operate as a diode in response to a control signal in a first state applied to the enable terminal and to operate as an open circuit in response to the control signal in a second state applied to the enable terminal. The levelling circuit is coupled to the connection terminal, the input terminal of the chip core, and the output terminal of the chip core.

公开(公告)号：US20130229875A1

公开(公告)日：2013-09-05

申请号：US13786202

申请日：2013-03-05

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Francesco La Rosa ,  Olivier Pizzuto ,  Stephan Niel ,  Philippe Boivin ,  Pascal Fornara ,  Laurent Lopez ,  Arnaud Regnier

IPC: G11C16/26 ,  G11C16/14

CPC classification number: G11C16/26 ,  G11C8/12 ,  G11C11/5642 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/7881

Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.

Abstract translation: 本公开涉及一种读取和写入存储单元的方法，每个存储单元包括与选择晶体管串联的电荷累积晶体管，包括将选择电压施加到存储器单元的选择晶体管的栅极; 将读取电压施加到存储单元的电荷累积晶体管的控制栅极; 将选择电压施加到耦合到相同位线的第二存储器单元的选择晶体管的栅极; 以及向第二存储单元的电荷累积晶体管的控制栅极施加抑制电压，以保持晶体管处于阻塞状态。

公开(公告)号：US11133798B2

公开(公告)日：2021-09-28

申请号：US16856448

申请日：2020-04-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Froidevaux ,  Laurent Lopez

IPC: H03K17/687 ,  H03K17/30

Abstract: A device includes a first connection pin, a second connection pin, a third connection pin, and a fourth connection pin. The second connection pin is configured to be connected to a supply voltage. The fourth connection pin is configured to be coupled to a reference voltage. The device further includes a first transistor including: a first gate and a first source/drain coupled to the first connection pin; a second transistor including a second gate and a second source/drain connected to the first transistor; and a third transistor including a third gate, a third source/drain connected to the second transistor, and a fourth source/drain connected to the fourth connection pin. The third transistor is configured to be controlled by a digital signal using the third connection pin. Both the first gate and the second gate are directly connected to the second connection pin.

公开(公告)号：US11680835B2

公开(公告)日：2023-06-20

申请号：US17155880

申请日：2021-01-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Froidevaux ,  Laurent Lopez

IPC: G01F1/60 ,  H03K5/01

CPC classification number: G01F1/60 ,  H03K5/01

Abstract: An oscillating analog signal includes a succession of dampened oscillations. That oscillating analog signal is conditioned to generate an output signal including only oscillations of the oscillating analog signal which have an amplitude smaller than a first threshold. The output signal is then processed by a processing unit, where the first threshold is compatible with a maximum level of voltage tolerable by the processing unit.

公开(公告)号：US12081204B2

公开(公告)日：2024-09-03

申请号：US17885086

申请日：2022-08-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Laurent Lopez

IPC: H03K17/16

CPC classification number: H03K17/161

Abstract: A power switch device includes a first terminal intended to be connected to a source of a first supply potential, a second terminal configured to supply a second potential, and a third terminal intended to be connected to a second source of a third supply potential. The device includes a first PMOS transistor having a source connected to the second terminal and a drain connected to the third terminal, a second PMOS transistor having a source connected to the second terminal, and a third PMOS transistor having a source connected to the first terminal and a drain connected to the drain of the second transistor. A control circuit generates gate control signals to control operation of the first, second and third PMOS transistors dependent on the first, second, and third supply potentials.

公开(公告)号：US11509305B2

公开(公告)日：2022-11-22

申请号：US17411838

申请日：2021-08-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Froidevaux ,  Laurent Lopez

IPC: H03K17/687 ,  H03K17/30

Abstract: An electronic chip includes a chip core including an input terminal, an output terminal, an external pad, and an input-output circuit coupled to the chip core and the external pad. The input-output circuit includes an enable terminal coupled to the chip core, a connection terminal coupled to the external pad, a switchable diode device coupled between a supply voltage and a reference voltage, and a levelling circuit. The switchable diode device is coupled to the connection terminal and the enable terminal and is configured to operate as a diode in response to a control signal in a first state applied to the enable terminal and to operate as an open circuit in response to the control signal in a second state applied to the enable terminal. The levelling circuit is coupled to the connection terminal, the input terminal of the chip core, and the output terminal of the chip core.

公开(公告)号：US08830761B2

公开(公告)日：2014-09-09

申请号：US13786202

申请日：2013-03-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Olivier Pizzuto ,  Stephan Niel ,  Philippe Boivin ,  Pascal Fornara ,  Laurent Lopez ,  Arnaud Regnier

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/34 ,  G11C16/14 ,  G11C16/08 ,  H01L29/423 ,  H01L29/788 ,  H01L27/115 ,  G11C16/04 ,  G11C11/56 ,  G11C8/12

CPC classification number: G11C16/26 ,  G11C8/12 ,  G11C11/5642 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/7881

Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.

Abstract translation: 本公开涉及一种读取和写入存储单元的方法，每个存储单元包括与选择晶体管串联的电荷累积晶体管，包括将选择电压施加到存储器单元的选择晶体管的栅极; 将读取电压施加到存储单元的电荷累积晶体管的控制栅极; 将选择电压施加到耦合到相同位线的第二存储器单元的选择晶体管的栅极; 以及向第二存储单元的电荷累积晶体管的控制栅极施加抑制电压，以保持晶体管处于阻塞状态。

公开(公告)号：US20130092987A1

公开(公告)日：2013-04-18

申请号：US13649972

申请日：2012-10-11

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Laurent Lopez

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/4983 ,  H01L21/28035

Abstract: A MOS transistor formed in an active area of a semiconductor substrate and having a polysilicon gate doped according to a first conductivity type, the gate including two lateral regions of the second conductivity type.

Abstract translation: 一种MOS晶体管，形成在半导体衬底的有源区中，并具有根据第一导电类型掺杂的多晶硅栅极，该栅极包括第二导电类型的两个横向区域。