公开(公告)号：US20220271030A1

公开(公告)日：2022-08-25

申请号：US17741900

申请日：2022-05-11

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Mohamed BOUFNICHEL

IPC: H01L27/08 ,  H01L27/06 ,  H01L49/02

Abstract: The present disclosure concerns an integrated circuit comprising a substrate, the substrate comprising a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the circuit comprising a three-dimensional capacitor formed inside and on top of the first region, and at least first and second connection terminals formed on the second region, the first and second connection terminals being respectively connected to first and second electrodes of the three-dimensional capacitor.

公开(公告)号：US20240128311A1

公开(公告)日：2024-04-18

申请号：US18357898

申请日：2023-07-24

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Mohamed BOUFNICHEL

IPC: H01G4/33 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L28/91 ,  H01L21/0217 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L28/92

Abstract: The present disclosure relates to a capacitor including a first conductive layer over which is formed a stack, comprising from the upper face of the first layer, a first electrode, a first dielectric layer, a second electrode, and a second conductive layer, the stack comprising a stair step within the second conductive layer, the second electrode, and a part of the thickness of the first dielectric layer, the stair step being filled with a second dielectric layer so that the sidewalls of the first electrode are aligned with respect to the sidewalls of the second dielectric layer.

公开(公告)号：US20210098444A1

公开(公告)日：2021-04-01

申请号：US17028732

申请日：2020-09-22

Applicant: STMicroelectronics (Tours) SAS

Inventor： Mohamed BOUFNICHEL

IPC: H01L27/02 ,  H01L29/06 ,  H01L21/762

Abstract: Methods and devices for protecting against electrical discharges are provided. One such device for protecting against electrical discharges includes a semiconductor substrate and an isolation trench in the semiconductor substrate. The isolation trench includes an enclosed space that contains a gas.

公开(公告)号：US20200091470A1

公开(公告)日：2020-03-19

申请号：US16692367

申请日：2019-11-22

Applicant: STMicroelectronics (Tours) SAS

Inventor： Julien LADROUE ,  Mohamed BOUFNICHEL

IPC: H01M2/06 ,  H01M2/30 ,  H01M2/02 ,  H01M2/20 ,  H01M10/058

Abstract: A battery structure has structure anode and cathode contacts on a front face and on a rear face. The battery structure includes a battery having battery anode and cathode contacts only on a front face thereof. A film including a conductive layer and an insulating layer jackets the battery. The conductive layer extends over the battery anode and cathode contacts and is interrupted therebetween. Openings are provided in the insulating layer on the front and rear faces of the battery structure to form the structure anode and cathode contacts of the battery structure.

公开(公告)号：US20230215733A1

公开(公告)日：2023-07-06

申请号：US18148329

申请日：2022-12-29

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Mohamed BOUFNICHEL

IPC: H01L21/308 ,  H01L21/306

CPC classification number: H01L21/3086 ,  H01L21/30604

Abstract: The present description concerns a method of forming a cavity in a substrate comprising: the forming of an etch mask comprising, opposite the location of the cavity, a plurality of sets of openings, the ratio between the openings and the mask of each set being selected according to the desired profile of the cavity opposite the surface of the mask having the set inscribed therein; and the wet etching of the substrate through the openings.

公开(公告)号：US20220190103A1

公开(公告)日：2022-06-16

申请号：US17542170

申请日：2021-12-03

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Mohamed BOUFNICHEL

IPC: H01L49/02

Abstract: The present description concerns a capacitor manufacturing method, including the successive steps of: a) forming a stack including, in the order from the upper surface of a substrate, a first conductive layer made of aluminum or an aluminum-based alloy, a first electrode, a first dielectric layer, and a second electrode; b) etching, by chemical plasma etching, an upper portion of the stack, said chemical plasma etching being interrupted before the upper surface of the first conductive layer; and c) etching, by physical plasma etching, a lower portion of the stack, said physical plasma etching being interrupted on the upper surface of the first conductive layer.

公开(公告)号：US20220311078A1

公开(公告)日：2022-09-29

申请号：US17839196

申请日：2022-06-13

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Mohamed BOUFNICHEL

IPC: H01M50/209 ,  H01M10/46 ,  H01M10/04 ,  H01M10/42 ,  H01M10/44 ,  H01M50/10 ,  H01M50/116 ,  H01M50/124 ,  H01M50/502

Abstract: The disclosure relates to microbattery devices and assemblies. In an embodiment, a device includes a plurality of microbatteries, a first flexible encapsulation film, and a second flexible encapsulation film. Each of the microbatteries includes a first contact terminal and a second contact terminal spaced apart from one another. The first flexible encapsulation film includes a first conductive layer electrically coupled to the first contact terminal of each of the microbatteries, and a first insulating layer on the first conductive layer. The second flexible encapsulation film includes a second conductive layer electrically coupled to the second contact terminal of each of the microbatteries, and a second insulating layer on the second conductive layer.

公开(公告)号：US20200286886A1

公开(公告)日：2020-09-10

申请号：US16801038

申请日：2020-02-25

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Mohamed BOUFNICHEL

IPC: H01L27/08 ,  H01L49/02 ,  H01L27/06

Abstract: The present disclosure concerns an integrated circuit comprising a substrate, the substrate comprising a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the circuit comprising a three-dimensional capacitor formed inside and on top of the first region, and at least first and second connection terminals formed on the second region, the first and second connection terminals being respectively connected to first and second electrodes of the three-dimensional capacitor.

公开(公告)号：US20190019687A1

公开(公告)日：2019-01-17

申请号：US16033334

申请日：2018-07-12

Applicant: STMicroelectronics (Tours) SAS

Inventor： Mathieu ROUVIERE ,  Mohamed BOUFNICHEL ,  Eric LACONDE

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/3105

Abstract: Laterally insulated integrated circuit chips are fabricated from a semiconductor wafer. Peripheral trenches are formed in the wafer which laterally delimit integrated circuit chips to be formed. A depth of the peripheral trenches is greater than or equal to a desired final thickness of the integrated circuit chips. The peripheral trenches are formed by a process which repeats successive steps of a) ion etching using a sulfur hexafluoride plasma, and b) passivating using an octafluorocyclobutane plasma. Upon completion of the step of forming the peripheral trenches, lateral walls of the peripheral trenches are covered by an insulating layer of a polyfluoroethene. A thinning step is performed on the lower surface of the wafer until a bottom of the peripheral trenches is reached. The insulating layer is not removed.

公开(公告)号：US20220310326A1

公开(公告)日：2022-09-29

申请号：US17839189

申请日：2022-06-13

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Mohamed BOUFNICHEL

IPC: H01G4/30 ,  H01G4/224 ,  H01L49/02 ,  H01G4/33

Abstract: A vertical capacitor includes a stack of layers conformally covering walls of a first material. The walls extend from a substrate made of a second material different from the first material.