公开(公告)号：US20200321329A1

公开(公告)日：2020-10-08

申请号：US16834499

申请日：2020-03-30

Applicant: STMicroelectronics (Tours) SAS

Inventor： Eric LACONDE ,  Olivier ORY

IPC: H01L27/02 ,  H01L27/08

Abstract: A device of protection against electrostatic discharges is formed in a semiconductor substrate of a first conductivity type that is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is positioned at an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are formed in the semiconductor layer and a region of the second conductivity type is formed in the second well. A stop channel region of the second conductivity type is provided in the semiconductor layer to laterally separating the first well from the second well, where no contact is present between this stop channel region and either of the first and second wells.

公开(公告)号：US20240063162A1

公开(公告)日：2024-02-22

申请号：US18497691

申请日：2023-10-30

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Olivier ORY ,  Christophe LEBRERE

IPC: H01L23/00 ,  H01L25/10

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/11916 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2224/8185

Abstract: The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 μm, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.

公开(公告)号：US20200321330A1

公开(公告)日：2020-10-08

申请号：US16834329

申请日：2020-03-30

Applicant: STMicroelectronics (Tours) SAS

Inventor： Eric LACONDE ,  Olivier ORY

IPC: H01L27/02 ,  H01L29/87 ,  H01L29/866

Abstract: A semiconductor substrate of a first conductivity type is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is formed an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are provided in the semiconductor layer. A second region of the second conductivity type is formed in the first well. A third region of the second conductivity type is formed in the second well. The first well, the semiconducting layer, the second well and the third region form a first lateral thyristor. The second well, the semiconductor layer, the first well and the second region form a second lateral thyristor. The buried region and semiconductor substrate form a zener diode which sets the trigger voltage for the lateral thyristors.

公开(公告)号：US20230021534A1

公开(公告)日：2023-01-26

申请号：US17858797

申请日：2022-07-06

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Olivier ORY ,  Philippe RABIER

IPC: H01L21/84 ,  H01L21/768 ,  H01L21/762 ,  H01L23/528 ,  H01L21/304 ,  H01L21/66

Abstract: The present description concerns an electronic die manufacturing method comprising: a) the deposition of an electrically-insulating resin layer on the side of a first surface of a semiconductor substrate, inside and on top of which have been previously formed a plurality of integrated circuits, the semiconductor substrate supporting on a second surface, opposite to the first surface, contacting pads; and b) the forming, on the side of the second surface of the semiconductor substrate, of first trenches, electrically separating the integrated circuits from one another, the first trenches vertically extending in the semiconductor substrate and emerging into or on top of the resin layer.

公开(公告)号：US20200075445A1

公开(公告)日：2020-03-05

申请号：US16552464

申请日：2019-08-27

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Olivier ORY ,  Romain JAILLET

IPC: H01L23/31 ,  H01L29/861 ,  H01L21/56 ,  H01L21/78

Abstract: The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.

公开(公告)号：US20230178380A1

公开(公告)日：2023-06-08

申请号：US18153929

申请日：2023-01-12

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Michael DE CRUZ ,  Olivier ORY

IPC: H01L21/48 ,  H01L21/56

CPC classification number: H01L21/4853 ,  H01L21/56

Abstract: A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.

公开(公告)号：US20220068866A1

公开(公告)日：2022-03-03

申请号：US17458070

申请日：2021-08-26

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Olivier ORY ,  Christophe LEBRERE

IPC: H01L23/00 ,  H01L25/10

Abstract: The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 μm, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.

公开(公告)号：US20220020652A1

公开(公告)日：2022-01-20

申请号：US17491189

申请日：2021-09-30

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Olivier ORY ,  Romain JAILLET

IPC: H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L29/861

Abstract: The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.

公开(公告)号：US20210043622A1

公开(公告)日：2021-02-11

申请号：US16987066

申请日：2020-08-06

Applicant: STMicroelectronics (Tours) SAS

Inventor： Olivier ORY

IPC: H01L27/02 ,  H01L29/06

Abstract: The present disclosure provides an electronic device that includes a substrate. The substrate includes a well and a peripheral insulating wall laterally surrounding the well. At least one lateral bipolar transistor is formed in the well, and the at least one transistor has a base region extending under parallel collector and emitter regions. The peripheral insulating wall is widened in a first direction, parallel to the collector and emitter regions, so that the base region penetrates into the peripheral insulating wall.

公开(公告)号：US20230068222A1

公开(公告)日：2023-03-02

申请号：US17896707

申请日：2022-08-26

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Olivier ORY ,  Michael DE CRUZ

IPC: H01L23/31 ,  H01L23/00

Abstract: The present disclosure relates to a method for manufacturing electronic chips comprising, in order: a. forming metal contacts on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits have been previously formed; b. depositing a first protective resin on the metal contacts and the first face of the semiconductor substrate; c. forming first trenches of a first width on the side of a second face of the semiconductor substrate; d. depositing a second protective resin in the first trenches and on the second face of the semiconductor substrate; e. forming second trenches of a second width, less than the first width, opposite the first trenches up to the metal contacts; and f. forming third trenches opposite the second trenches, the third trenches extending through the metal contacts.