公开(公告)号：US09673057B2

公开(公告)日：2017-06-06

申请号：US14665815

申请日：2015-03-23

Applicant: Lam Research Corporation

Inventor： In Deog Bae ,  Qian Fu

IPC: H01L21/311 ,  H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C03C1/00 ,  H01L39/24 ,  H01L21/3065 ,  H01L21/306 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/3105 ,  H01L27/11548 ,  H01L27/11573

CPC classification number: H01L21/31116 ,  H01L21/30604 ,  H01L21/30655 ,  H01L21/31055 ,  H01L21/31138 ,  H01L21/31144 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L39/247 ,  H01L2224/11916

Abstract: A method for forming a stair-step structure in a substrate within a plasma processing chamber is provided. An organic mask is formed over the substrate. The organic mask is trimmed with a vertical to lateral ratio of less than 0.8, wherein the trimming simultaneously forms a deposition over the organic mask. The substrate is etched. The steps of trimming the organic mask and etching the substrate are cyclically repeated a plurality of times.

公开(公告)号：US20130224946A1

公开(公告)日：2013-08-29

申请号：US13854321

申请日：2013-04-01

Applicant: Infineon Technologies AG

Inventor： Thomas Goebel ,  Erdem Kaltalioglu ,  Markus Naujok

IPC: H01L21/768

CPC classification number: H01L24/11 ,  H01L21/76885 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/11 ,  H01L2224/11916 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

Abstract: A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels.

公开(公告)号：US09552987B2

公开(公告)日：2017-01-24

申请号：US14297661

申请日：2014-06-06

Applicant: TOKYO ELECTRON LIMITED

Inventor： Yuichiro Miyata ,  Keiichi Tanaka ,  Kenichi Ueda ,  Takahiro Shiozawa

IPC: H01L21/311 ,  H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  H01L21/027 ,  H01L21/02 ,  H01L21/67 ,  G03F7/42 ,  H01L21/768

CPC classification number: H01L21/0273 ,  G03F7/422 ,  H01L21/02065 ,  H01L21/31133 ,  H01L21/67115 ,  H01L21/6715 ,  H01L21/7684 ,  H01L2224/11916

Abstract: A substrate processing method is performed to improve surface roughness of a pattern mask formed on a substrate by being exposed and developed. The method includes supplying a first solvent in a gaseous state to a surface of the substrate to dissolve the pattern mask, and supplying a second solvent to the surface of the substrate, which is supplied with the first solvent, to dissolve the pattern mask, wherein a permeability of the second solvent is lower than a permeability of the first solvent.

Abstract translation: 进行基板处理方法，以通过曝光和显影来改善形成在基板上的图案掩模的表面粗糙度。 该方法包括将气态的第一溶剂供给到基板的表面以溶解图案掩模，并将第二溶剂供应到提供有第一溶剂的基板的表面以溶解图案掩模，其中 第二溶剂的渗透性低于第一溶剂的渗透性。

公开(公告)号：US09397058B2

公开(公告)日：2016-07-19

申请号：US14563448

申请日：2014-12-08

Applicant: STATS ChipPAC, Ltd.

Inventor： Xusheng Bao ,  Ma Phoo Pwint Hlaing ,  Jian Zuo

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L23/525

CPC classification number: H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0332 ,  H01L2224/034 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/035 ,  H01L2224/03505 ,  H01L2224/0361 ,  H01L2224/03632 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/05086 ,  H01L2224/05088 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05687 ,  H01L2224/1111 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11466 ,  H01L2224/118 ,  H01L2224/11849 ,  H01L2224/11916 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13078 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13553 ,  H01L2224/1357 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/01013 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/00013 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2924/01023 ,  H01L2924/04941 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.

公开(公告)号：US20150228690A1

公开(公告)日：2015-08-13

申请号：US14691243

申请日：2015-04-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-De Wang ,  Shuang-Ji Tsai ,  Yueh-Chiou Lin

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14683 ,  H01L27/14685 ,  H01L27/14689 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/11916 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/83359 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.

Abstract translation: 集成电路结构包括半导体衬底和从半导体衬底的底表面延伸到半导体衬底中的介质衬垫。 低k电介质层设置在半导体衬底下方。 第一个非低k电介质层位于低k电介质层的下面。 金属焊盘位于第一非低k电介质层的下面。 第二个非低k电介质层位于金属焊盘的下方。 开口从半导体衬底的顶表面向下延伸以穿透半导体衬底，电介质衬垫和低k电介质层，其中，开口焊接在金属衬垫的顶表面上。 钝化层包括在开口的侧壁上的部分，其中去除开口底部的钝化层的一部分。

公开(公告)号：US20150091165A1

公开(公告)日：2015-04-02

申请号：US14563448

申请日：2014-12-08

Applicant: STATS ChipPAC, Ltd.

Inventor： Xusheng Bao ,  Ma Phoo Pwint Hlaing ,  Jian Zuo

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0332 ,  H01L2224/034 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/035 ,  H01L2224/03505 ,  H01L2224/0361 ,  H01L2224/03632 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/05086 ,  H01L2224/05088 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05687 ,  H01L2224/1111 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11466 ,  H01L2224/118 ,  H01L2224/11849 ,  H01L2224/11916 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13078 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13553 ,  H01L2224/1357 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/01013 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/00013 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2924/01023 ,  H01L2924/04941 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.

Abstract translation: 半导体器件具有在半导体晶片的表面上形成有第一导电层的半导体晶片。 在半导体晶片和第一导电层的表面上形成第一绝缘层。 在第一绝缘层和第一导电层上形成第二导电层。 在第一绝缘层和第二导电层上形成第二绝缘层。 在半导体晶片的凸块形成区域中的第二绝缘层中形成多个开口以暴露第二导电层并减少电迁移的不利影响。 开口由第二绝缘层的一部分分开。 UBM层形成在电连接到第二导电层的凸块形成区域中的第二绝缘层的开口上方。 在UBM层上形成凸点。

公开(公告)号：US20140363976A1

公开(公告)日：2014-12-11

申请号：US14297661

申请日：2014-06-06

Applicant: TOKYO ELECTRON LIMITED

Inventor： Yuichiro MIYATA ,  Keiichi TANAKA ,  Kenichi UEDA ,  Takahiro SHIOZAWA

IPC: H01L21/3105 ,  H01L21/67

CPC classification number: H01L21/0273 ,  G03F7/422 ,  H01L21/02065 ,  H01L21/31133 ,  H01L21/67115 ,  H01L21/6715 ,  H01L21/7684 ,  H01L2224/11916

Abstract: A substrate processing method is performed to improve surface roughness of a pattern mask formed on a substrate by being exposed and developed. The method includes supplying a first solvent in a gaseous state to a surface of the substrate to dissolve the pattern mask, and supplying a second solvent to the surface of the substrate, which is supplied with the first solvent, to dissolve the pattern mask, wherein a permeability of the second solvent is lower than a permeability of the first solvent.

Abstract translation: 进行基板处理方法，以通过曝光和显影来改善形成在基板上的图案掩模的表面粗糙度。 该方法包括将气态的第一溶剂供给到基板的表面以溶解图案掩模，并将第二溶剂供应到提供有第一溶剂的基板的表面以溶解图案掩模，其中 第二溶剂的渗透性低于第一溶剂的渗透性。

公开(公告)号：US20140295661A1

公开(公告)日：2014-10-02

申请号：US14307263

申请日：2014-06-17

Applicant: Infineon Technologies AG

Inventor： Thomas Goebel ,  Erdem Kaltalioglu ,  Markus Naujok

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L21/76885 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/11 ,  H01L2224/11916 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

Abstract: A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels.

Abstract translation: 描述了形成钝化的铜芯片焊盘的结构和方法。 在各种实施例中，本发明描述了一种衬底，其包括设置在衬底上方的有源电路和金属电平。 钝化层设置在金属层的最后一层上方。 导电衬垫设置在设置在钝化层中的开口的侧壁中，其中导电衬垫也设置在金属水平的最后一级的暴露表面上。

公开(公告)号：US11824028B2

公开(公告)日：2023-11-21

申请号：US17458070

申请日：2021-08-26

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Olivier Ory ,  Christophe Lebrere

IPC: H01L25/10 ,  H01L23/00

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/11916 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/8185 ,  H01L2224/81801

Abstract: The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 μm, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.

公开(公告)号：US20230245988A1

公开(公告)日：2023-08-03

申请号：US18058006

申请日：2022-11-22

Applicant: Apple Inc.

Inventor： Kwan-Yu Lai ,  Kunzhong Hu ,  Jun Zhai ,  Young Doo Jeon

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/73 ,  H01L24/13 ,  H01L24/20 ,  H01L24/19 ,  H01L24/14 ,  H01L2224/73101 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/19 ,  H01L2224/11002 ,  H01L2224/11916 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/1184 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13018 ,  H01L2224/13075 ,  H01L2224/13541 ,  H01L2224/13552 ,  H01L2224/13575 ,  H01L2924/35121

Abstract: Die reconstitution methods and dies with reconstituted contact bumps are described. In an embodiment, a die reconstitution method includes reconstituting a plurality of dies including first contact bumps of a first type, partially removing the first contact bumps, and forming second contact bumps of a second type on top of the partially removed first contact bumps, where the second type is different than the first type.