公开(公告)号：US20250075370A1

公开(公告)日：2025-03-06

申请号：US18811164

申请日：2024-08-21

Applicant: STMicroelectronics International N.V.

Inventor： Björn MAGNUSSON LINDGREN ,  Mathias ISACSON

IPC: C30B29/36 ,  C30B25/18

Abstract: A structure including a base portion (e.g., made of a graphite-based or graphene-based material) with at least one surface that is coated with a homogenous coating layer (e.g., made of silicon-carbide (SiC)). The homogenous coating layer prevents contaminants (e.g., carbon) from being released by the base portion into a cavity of a processing tool when heated to process one or more workpieces (e.g., silicon substrate, silicon wafers, etc.) present within the cavity. The homogenous coating layer includes grains and grain boundaries that are relatively the same size and shape as each other, which further prevents propagation of defects (e.g., cracking, peeling, etc.) that could potentially cause exposure of a region of the first surface of the base portion to the cavity of the processing tool contaminating the one or more workpieces present within the cavity of the processing tool.

公开(公告)号：US20240332365A1

公开(公告)日：2024-10-03

申请号：US18614485

申请日：2024-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Björn MAGNUSSON LINDGREN ,  Carlo RIVA

IPC: H01L29/16 ,  C30B28/14 ,  C30B29/36 ,  H01L21/02 ,  H01L29/04

CPC classification number: H01L29/1608 ,  C30B28/14 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/0262 ,  H01L29/04

Abstract: Various embodiments of wafers include a polycrystalline silicon carbide (SiC) layer or base substrate. The polycrystalline silicon carbide (SiC) layer may have a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter) such that the polycrystalline silicon carbide layer is a low resistivity polycrystalline silicon carbide layer. The polycrystalline silicon carbide layer may have grains with a grain size less than or equal to 1 millimeter (mm), and may have a non-columnar structure. The polycrystalline silicon carbide layer may have a warpage less than or equal to 75 μm (micrometers). A monocrystalline silicon carbide (SiC) layer may be coupled to the polycrystalline silicon carbide (SiC) layer by a bonding layer. The monocrystalline silicon carbide layer may be thinner than the polycrystalline silicon carbide layer.

公开(公告)号：US20240332011A1

公开(公告)日：2024-10-03

申请号：US18614538

申请日：2024-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Björn MAGNUSSON LINDGREN ,  Alexandre ELLISON ,  Carlo RIVA

IPC: H01L21/02 ,  C30B28/14 ,  C30B29/36

CPC classification number: H01L21/02378 ,  C30B28/14 ,  C30B29/36 ,  H01L21/02433 ,  H01L21/0262

Abstract: At least one embodiment of a method of manufacturing includes forming a first polycrystalline silicon carbide (SiC) substrate with a sintering process by sintering one or more powdered semiconductor materials. After the first polycrystalline SiC substrate is formed utilizing the sintering process, the first polycrystalline silicon carbide SiC substrate is utilized to form a second polycrystalline SiC substrate with a chemical vapor deposition (CVD) process. The second polycrystalline SiC substrate is formed on a surface of the first polycrystalline SiC substrate by depositing SiC on the surface of the first polycrystalline SiC substrate with the CVD process. As the first and second polycrystalline SiC substrates are made of the same or similar semiconductor material (e.g., SiC), a first coefficient of thermal expansion (CTE) for the first polycrystalline SiC substrate is the same or similar to the second CTE of the second polycrystalline SiC substrate.

公开(公告)号：US20250105004A1

公开(公告)日：2025-03-27

申请号：US18887762

申请日：2024-09-17

Applicant: STMicroelectronics International N.V.

Inventor： Björn MAGNUSSON LINDGREN ,  Niclas KARLSSON ,  Esa HÄMÄLÄINEN ,  Alexandre ELLISON

IPC: H01L21/02 ,  C30B28/14 ,  C30B29/36

Abstract: A polycrystalline SiC wafer or substrate with a high resistivity benefits functionality of a high power electronic or system in which the polycrystalline SiC wafer or substrate is present or is utilized in manufacturing the high power electronic or system. At least one embodiment of a wafer includes a polycrystalline SiC wafer or substrate that has a high resistivity (e.g., equal to or greater than 1*10{circumflex over ( )}5 or 1E+5 ohm-centimeters) and low warpage. Electronic devices or components made with or from the wafer including the high resistivity polycrystalline SiC wafer or substrate are further optimized when in use and have fewer to no crystal defects. The wafer formed according to the embodiments of the present disclosure has a high or very high resistivity as compared to existing polycrystalline SiC wafers or substrate.

公开(公告)号：US20240332366A1

公开(公告)日：2024-10-03

申请号：US18614522

申请日：2024-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Björn MAGNUSSON LINDGREN ,  Carlo RIVA

IPC: H01L29/16 ,  C30B28/02 ,  C30B29/36 ,  C30B33/02 ,  H01L21/02 ,  H01L29/04

CPC classification number: H01L29/1608 ,  C30B28/02 ,  C30B29/36 ,  C30B33/02 ,  H01L21/02378 ,  H01L21/02433 ,  H01L29/04

Abstract: A polycrystalline silicon carbide (SiC) substrate with a density gradient between a first side of the polycrystalline SiC substrate and a second side of the polycrystalline SiC substrate opposite to the first side. A first density at the first side of the polycrystalline SiC substrate is less than a second density at the second side of the polycrystalline SiC substrate. The polycrystalline SiC substrate with the density gradient may be formed by forming a polycrystalline SiC base substrate with a sintering process followed by a post-sintering process. For example, the post sintering process may be at least one of the following of: applying a first temperature to the first side and a second temperature to the second side of the polycrystalline SiC substrate and performing a chemical vapor deposition (CVD) process to impregnate further silicon (Si) and carbon (C) atoms into the polycrystalline SiC base substrate.