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公开(公告)号：US20230065623A1
公开(公告)日：2023-03-02
申请号：US17815807
申请日：2022-07-28
Inventor： Vivek Mohan Sharma , Roberto Colombo
Abstract: A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.
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公开(公告)号：US11764807B2
公开(公告)日：2023-09-19
申请号：US17858782
申请日：2022-07-06
Inventor： Vivek Mohan Sharma , Roberto Colombo
CPC classification number: H03M13/1105 , H03M13/611
Abstract: A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits. For example the safety monitor circuit comprises a test circuit configured to provide modified data bits and/or modified ECC bits to the error detection circuit as a function of connectivity test control signals, whereby the error detection circuit asserts the error signal as a function of the connectivity test control signals. The processing system comprises also a connectivity test control circuit comprising control registers programmable via the microprocessor, wherein the connectivity test control signals are generated as a function of the content of the control registers.
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公开(公告)号：US20220334865A1
公开(公告)日：2022-10-20
申请号：US17657856
申请日：2022-04-04
Inventor： Roberto Colombo , Vivek Mohan Sharma
Abstract: A processing system includes safety monitoring circuits configured to generate error signals by monitoring a microprocessor operations, a memory controller, and/or a resource. The system further includes fault collection sub-circuits, each including one or more error combination circuits, each including a first programmable register and being configured to receive a subset of the error signals, determine whether an error signal is asserted, and store to the first register error status data that identifies the asserted error signal. Each error combination circuit is configured to read enable data from the first register and generate a combined error signal based on the error status and enable data. The error management circuit includes a second programmable register and is configured to receive the combined error signals, read routing data from the second register, and generate for each microprocessor an error signal based on the combined error signals and routing data.
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公开(公告)号：US20220122682A1
公开(公告)日：2022-04-21
申请号：US17567481
申请日：2022-01-03
Applicant: STMicroelectronics International N.V.
Inventor： Vivek Mohan Sharma , Deepak Baranwal , Nicolas Bernard Grossier , Samiksha Agarwal
Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first error packet associated with a first circuit; receiving, with the first buffer, a second error packet associated with a second circuit; transmitting a first reading request for reading the first error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central error management circuit; in response to receiving the first reading request, reading the first error packet from the first buffer, transmitting the first error packet to a controller of the central error management circuit, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second error packet.
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公开(公告)号：US12253562B2
公开(公告)日：2025-03-18
申请号：US18186624
申请日：2023-03-20
Inventor： Roberto Colombo , Vivek Mohan Sharma
IPC: G06F1/24 , G01R31/317 , G01R31/3185 , G06F11/14
Abstract: In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.
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Patent Agency Ranking
公开(公告)号：US11217323B1
公开(公告)日：2022-01-04
申请号：US17010272
申请日：2020-09-02
Applicant: STMicroelectronics International N.V.
Inventor： Vivek Mohan Sharma , Deepak Baranwal , Nicolas Bernard Grossier , Samiksha Agarwal
Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first memory error packet associated with a first memory; receiving, with the first buffer, a second memory error packet associated with a second memory; transmitting a first reading request for reading the first memory error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central memory error management unit (MEMU); in response to receiving the first reading request, reading the first memory error packet from the first buffer, transmitting the first memory error packet to a controller of the central MEMU, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second memory error packet.
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公开(公告)号：US12061530B2
公开(公告)日：2024-08-13
申请号：US17655103
申请日：2022-03-16
Inventor： Roberto Colombo , Vivek Mohan Sharma
IPC: G06F11/22 , G06F11/07 , G06F11/273
CPC classification number: G06F11/2273 , G06F11/0772 , G06F11/079 , G06F11/2733
Abstract: A processing system includes a processing core including a microprocessor, a memory controller configured to read software instructions for execution by the processing core, a plurality of safety monitoring circuits configured to generate a plurality of error signals by monitoring operation of the processing core and the memory controller, a fault collection and error management circuit implemented as a hardware circuit, and a connectivity test circuit. The fault collection and error management circuit is configured to receive the plurality of error signals from the plurality of safety monitoring circuits and generate one or more reaction signals as a function of the plurality of error signals. The connectivity test circuit is configured to, during a diagnostic phase executed by the processing system after executing a reset phase and before executing a software runtime phase, test connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit.
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公开(公告)号：US20230349969A1
公开(公告)日：2023-11-02
申请号：US18186549
申请日：2023-03-20
Inventor： Roberto Colombo , Vivek Mohan Sharma , Samiksha Agarwal
IPC: G01R31/317
CPC classification number: G01R31/31703 , G01R31/31722
Abstract: In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.
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公开(公告)号：US11749367B2
公开(公告)日：2023-09-05
申请号：US17567481
申请日：2022-01-03
Applicant: STMicroelectronics International N.V.
Inventor： Vivek Mohan Sharma , Deepak Baranwal , Nicolas Bernard Grossier , Samiksha Agarwal
CPC classification number: G11C29/10 , G06F13/1605 , G06F13/1689 , G11C29/42 , G11C29/44 , G11C2029/4402
Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first error packet associated with a first circuit; receiving, with the first buffer, a second error packet associated with a second circuit; transmitting a first reading request for reading the first error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central error management circuit; in response to receiving the first reading request, reading the first error packet from the first buffer, transmitting the first error packet to a controller of the central error management circuit, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second error packet.
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公开(公告)号：US12068048B2
公开(公告)日：2024-08-20
申请号：US17815807
申请日：2022-07-28
Inventor： Vivek Mohan Sharma , Roberto Colombo
CPC classification number: G11C29/42 , G11C29/36 , G11C29/48 , G11C2029/3602
Abstract: A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.
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