公开(公告)号：US20240288478A1

公开(公告)日：2024-08-29

申请号：US18436644

申请日：2024-02-08

Applicant: STMicroelectronics International N.V.

Inventor： Antonio Barcella ,  Mario Rotigni ,  Nicolas Bernard Grossier

IPC: G01R23/00 ,  G01S19/13 ,  H03K5/26 ,  H03K19/20

CPC classification number: G01R23/005 ,  G01S19/13 ,  H03K5/26 ,  H03K19/20

Abstract: A method comprises receiving an input clock signal having a clock frequency band between a lower frequency limit value and an upper frequency limit value, dividing the clock frequency band in a set of frequency ranges having a set of frequency limit values that include the lower frequency limit value and the upper frequency limit value, comparing the frequency of the clock signal with the set of frequency limit values to produce comparison indicators having a first logic value when the measured frequency fails to exceed at least one frequency limit value and having a second logic value when the measured frequency exceeds the at least one frequency limit value, and, as a result of at least one of the logic values of comparison indicators having the second logic value, producing a global flag signal indicating that the measured frequency falls outside of a frequency range.

公开(公告)号：US20220122682A1

公开(公告)日：2022-04-21

申请号：US17567481

申请日：2022-01-03

Applicant: STMicroelectronics International N.V.

Inventor： Vivek Mohan Sharma ,  Deepak Baranwal ,  Nicolas Bernard Grossier ,  Samiksha Agarwal

IPC: G11C29/10 ,  G11C29/44 ,  G06F13/16 ,  G11C29/42

Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first error packet associated with a first circuit; receiving, with the first buffer, a second error packet associated with a second circuit; transmitting a first reading request for reading the first error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central error management circuit; in response to receiving the first reading request, reading the first error packet from the first buffer, transmitting the first error packet to a controller of the central error management circuit, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second error packet.

公开(公告)号：US11749367B2

公开(公告)日：2023-09-05

申请号：US17567481

申请日：2022-01-03

Applicant: STMicroelectronics International N.V.

Inventor： Vivek Mohan Sharma ,  Deepak Baranwal ,  Nicolas Bernard Grossier ,  Samiksha Agarwal

IPC: G11C16/06 ,  G11C29/10 ,  G11C29/44 ,  G06F13/16 ,  G11C29/42

CPC classification number: G11C29/10 ,  G06F13/1605 ,  G06F13/1689 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/4402

Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first error packet associated with a first circuit; receiving, with the first buffer, a second error packet associated with a second circuit; transmitting a first reading request for reading the first error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central error management circuit; in response to receiving the first reading request, reading the first error packet from the first buffer, transmitting the first error packet to a controller of the central error management circuit, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second error packet.

公开(公告)号：US11217323B1

公开(公告)日：2022-01-04

申请号：US17010272

申请日：2020-09-02

Applicant: STMicroelectronics International N.V.

Inventor： Vivek Mohan Sharma ,  Deepak Baranwal ,  Nicolas Bernard Grossier ,  Samiksha Agarwal

IPC: G11C16/06 ,  G11C29/10 ,  G11C29/44 ,  G06F13/16 ,  G11C29/42

Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first memory error packet associated with a first memory; receiving, with the first buffer, a second memory error packet associated with a second memory; transmitting a first reading request for reading the first memory error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central memory error management unit (MEMU); in response to receiving the first reading request, reading the first memory error packet from the first buffer, transmitting the first memory error packet to a controller of the central MEMU, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second memory error packet.

公开(公告)号：US12068057B2

公开(公告)日：2024-08-20

申请号：US18056803

申请日：2022-11-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V. ,  STMicroelectronics Application GMBH

Inventor： Asif Rashid Zargar ,  Nicolas Bernard Grossier ,  Charul Jain ,  Roberto Colombo

IPC: G11C7/24 ,  G11C7/10

CPC classification number: G11C7/24 ,  G11C7/1039 ,  G11C7/1069

Abstract: In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.

公开(公告)号：US11360143B2

公开(公告)日：2022-06-14

申请号：US17083876

申请日：2020-10-29

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： Avneep Kumar Goyal ,  Deepak Baranwal ,  Thomas Szurmant ,  Nicolas Bernard Grossier

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3193 ,  G06F11/34 ,  G01R31/319 ,  G06F11/36

Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.