公开(公告)号：US10128207B2

公开(公告)日：2018-11-13

申请号：US14674891

申请日：2015-03-31

Applicant: STMicroelectronics Pte Ltd

Inventor： Yun Liu ,  Jerome Teysseyre ,  Yonggang Jin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78

Abstract: One or more embodiments are directed to semiconductor packages that include a pillar and bump structures. The semiconductor packages include a die that has recess at a perimeter of the semiconductor die. The semiconductor package includes an encapsulation layer that is located over the semiconductor die filling the recess and surrounding side surfaces of the pillars. The package may be formed on a wafer with a plurality of die and may be singulated into a plurality of packages.

公开(公告)号：US08796139B2

公开(公告)日：2014-08-05

申请号：US13722776

申请日：2012-12-20

Applicant: STMicroelectronics Pte Ltd.

Inventor： Anandan Ramasamy ,  Yonggang Jin ,  Yun Liu

IPC: H01L21/44

CPC classification number: H01L21/565 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/96 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00

Abstract: A bar formed from a reconstituted wafer and containing one or more conductive material filled voids is used to electrically and physically connect the top and bottom packages in a package-on-package (PoP) package. The bar is disposed in the fan out area of the lower package forming the PoP package.

Abstract translation: 由重构的晶片形成并包含一个或多个导电材料填充的空隙的条被用于电和物理地连接封装在封装（PoP）封装中的顶部和底部封装。 该条被布置在形成PoP包装的下部包装的扇形区域中。

公开(公告)号：US08860228B2

公开(公告)日：2014-10-14

申请号：US13727206

申请日：2012-12-26

Applicant: STMicroelectronics Pte. Ltd

Inventor： Yonggang Jin ,  Yun Liu ,  Yaohuang Huang

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L24/19 ,  H01L23/3128 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2924/00

Abstract: An electronic device may include a bottom interconnect layer having a first electrically conductive via therein. The electronic device may also include an integrated circuit (IC) carried by said bottom interconnect layer, and an encapsulation material on the bottom interconnect layer and surrounding the IC. The encapsulation layer may have a second electrically conductive via therein aligned with the first electrically conductive via. The second electrically conductive via may have a cross-sectional area larger than a cross-sectional area of the first electrically conductive via.

Abstract translation: 电子器件可以包括其中具有第一导电通孔的底部互连层。 电子设备还可以包括由所述底部互连层承载的集成电路（IC）和在底部互连层上并围绕IC的封装材料。 封装层可以具有与第一导电通孔对准的第二导电通孔。 第二导电通孔的横截面积可以大于第一导电通孔的横截面面积。

公开(公告)号：US10910287B2

公开(公告)日：2021-02-02

申请号：US16270927

申请日：2019-02-08

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yun Liu ,  David Gani

IPC: H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L21/304 ,  H01L23/00 ,  H01L23/28

Abstract: A semiconductor package having a die with a sidewall protected by molding compound, and methods of forming the same are disclosed. The package includes a die with a first surface opposite a second surface and sidewalls extending between the first and second surfaces. A redistribution layer is formed on the first surface of each die. An area of the first surface of the die is greater than an area of the redistribution layer, such that a portion of the first surface of the die is exposed. When molding compound is formed over the die and the redistribution layer to form a semiconductor package, the molding compound is on the first surface of the die between an outer edge of the redistribution layer and an outer edge of the first surface. The molding compound is also on the sidewalls of the die, which provides protection against chipping or cracking during transport.

公开(公告)号：US11562937B2

公开(公告)日：2023-01-24

申请号：US17145028

申请日：2021-01-08

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yun Liu ,  David Gani

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/304 ,  H01L23/28

Abstract: A semiconductor package having a die with a sidewall protected by molding compound, and methods of forming the same are disclosed. The package includes a die with a first surface opposite a second surface and sidewalls extending between the first and second surfaces. A redistribution layer is formed on the first surface of each die. An area of the first surface of the die is greater than an area of the redistribution layer, such that a portion of the first surface of the die is exposed. When molding compound is formed over the die and the redistribution layer to form a semiconductor package, the molding compound is on the first surface of the die between an outer edge of the redistribution layer and an outer edge of the first surface. The molding compound is also on the sidewalls of the die, which provides protection against chipping or cracking during transport.

公开(公告)号：US20160293559A1

公开(公告)日：2016-10-06

申请号：US14674891

申请日：2015-03-31

Applicant: STMicroelectronics Pte Ltd

Inventor： Yun Liu ,  Jerome Teysseyre ,  Yonggang Jin

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/78 ,  H01L23/3178 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/11334 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11

Abstract: One or more embodiments are directed to semiconductor packages that include a pillar and bump structures. The semiconductor packages include a die that has recess at a perimeter of the semiconductor die. The semiconductor package includes an encapsulation layer that is located over the semiconductor die filling the recess and surrounding side surfaces of the pillars. The package may be formed on a wafer with a plurality of die and may be singulated into a plurality of packages.

Abstract translation: 一个或多个实施例涉及包括柱和凸块结构的半导体封装。 半导体封装包括在半导体管芯的周边具有凹部的管芯。 半导体封装包括封装层，该封装层位于半导体管芯上方，该封装层填充凹槽并且围绕柱的周围侧表面。 封装可以形成在具有多个管芯的晶片上，并且可以被单个化成多个封装。

公开(公告)号：US20130168858A1

公开(公告)日：2013-07-04

申请号：US13722776

申请日：2012-12-20

Applicant: STMicroelectronics Pte Ltd.

Inventor： Anandan Ramasamy ,  Yonggang Jin ,  Yun Liu

IPC: H01L21/56 ,  H01L23/498

CPC classification number: H01L21/565 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/96 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00

Abstract: A bar formed from a reconstituted wafer and containing one or more conductive material filled voids is used to electrically and physically connect the top and bottom packages in a package-on-package (PoP) package. The bar is disposed in the fan out area of the lower package forming the PoP package.

Abstract translation: 由重构的晶片形成并包含一个或多个导电材料填充的空隙的条被用于电和物理地连接封装在封装（PoP）封装中的顶部和底部封装。 该条被布置在形成PoP包装的下部包装的扇形区域中。

公开(公告)号：US20140175649A1

公开(公告)日：2014-06-26

申请号：US13727206

申请日：2012-12-26

Applicant: STMICROELECTRONICS PTE. LTD

Inventor： Yonggang Jin ,  Yun Liu ,  Yaohuang Huang

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L24/19 ,  H01L23/3128 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2924/00

Abstract: An electronic device may include a bottom interconnect layer having a first electrically conductive via therein. The electronic device may also include an integrated circuit (IC) carried by said bottom interconnect layer, and an encapsulation material on the bottom interconnect layer and surrounding the IC. The encapsulation layer may have a second electrically conductive via therein aligned with the first electrically conductive via. The second electrically conductive via may have a cross-sectional area larger than a cross-sectional area of the first electrically conductive via.

Abstract translation: 电子器件可以包括其中具有第一导电通孔的底部互连层。 电子设备还可以包括由所述底部互连层承载的集成电路（IC）和在底部互连层上并围绕IC的封装材料。 封装层可以具有与第一导电通孔对准的第二导电通孔。 第二导电通孔的横截面积可以大于第一导电通孔的横截面面积。