公开(公告)号：US20040037144A1

公开(公告)日：2004-02-26

申请号：US10438175

申请日：2003-05-13

Applicant: STMicroelectronics S.r.l.

Inventor： Luigi Pascucci ,  Paolo Rolandi ,  Marco Riva

IPC: G11C007/00

CPC classification number: G11C11/5628

Abstract: A method for programming a non-volatile memory device of the multi-level type, includes a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses. Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.

Abstract translation: 一种用于对多电平型非易失性存储器件进行编程的方法包括分组成存储字的多个晶体管单元，并且通常设置有栅极和漏极端子。 该方法在不同的阈值下应用不同的漏极电压值。 这些值与各个存储器字位要达到的阈值水平成正比，并有效地提供了在有限数量的脉冲结束时以寻求方式获得电平的电平 。 有利地，恒定栅极电压值同时施加到所述单元的栅极端子，使得单元编程时间与所寻求的阈值水平无关。

公开(公告)号：US20020196695A1

公开(公告)日：2002-12-26

申请号：US10158553

申请日：2002-05-30

Applicant: STMicroelectronics S.r.l.

Inventor： Luigi Pascucci

IPC: G11C008/00

CPC classification number: H01L27/115 ,  G11C7/1006 ,  G11C7/1048 ,  G11C16/0475 ,  G11C16/0491 ,  G11C2207/002

Abstract: The column multiplexer is for a memory matrix having memory cells arranged in rows and columns. The multiplexer includes input lines for input signals, a plurality of output lines for electrical connection to the columns of the matrix, a selective connection device for selecting, in a first operation mode, at least one output line of the plurality of output lines in such a way as to connect it selectively to the input lines. In the first operation mode, the selective connection device selects a first group of output lines among the plurality of output lines, including at least three first lines.

Abstract translation: 列多路复用器用于具有以行和列排列的存储单元的存储器矩阵。 多路复用器包括用于输入信号的输入线，用于电连接到矩阵列的多条输出线，用于在第一操作模式中选择多条输出线中至少一条输出线的选择性连接装置 一种将其选择性地连接到输入线的方式。 在第一操作模式中，选择连接装置选择包括至少三条第一行的多条输出线中的第一组输出线。

公开(公告)号：US20020196662A1

公开(公告)日：2002-12-26

申请号：US10158554

申请日：2002-05-30

Applicant: STMicroelectronics S.r.l.

Inventor： Luigi Pascucci

IPC: G11C016/04

CPC classification number: G11C16/26 ,  G11C16/0475 ,  G11C16/0491

Abstract: A memory system includes a memory matrix formed on a semiconductor structure. The memory matrix includes a first column line and a second column line which are connected electrically to at least one first memory cell to be read. For the reading of the at least one first cell, a first reading voltage can be supplied to the first column line. The memory matrix also includes a third column line distinct from the first column line and from the second column line. The memory matrix further includes generating circuit for supplying, to the third column line and during the reading of the at least one first memory cell, a biasing voltage which can oppose the establishment of an electric current between the first column line and the third column line in the semiconductor structure. The biasing voltage is preferably substantially equal to the first reading voltage.

Abstract translation: 存储器系统包括形成在半导体结构上的存储矩阵。 存储矩阵包括电连接到要读取的至少一个第一存储器单元的第一列线和第二列线。 为了读取至少一个第一单元，可以向第一列线提供第一读取电压。 存储器矩阵还包括与第一列线和第二列线不同的第三列线。 存储矩阵还包括产生电路，用于向第三列线提供并且在至少一个第一存储单元的读取期间提供偏置电压，该偏置电压可以反对在第一列线和第三列线之间建立电流 在半导体结构中。 偏置电压优选地基本上等于第一读取电压。

公开(公告)号：US20030101328A1

公开(公告)日：2003-05-29

申请号：US10245795

申请日：2002-09-16

Applicant: STMicroelectronics S.r.l.

Inventor： Luigi Pascucci

IPC: G06F012/00

CPC classification number: G06F12/0223 ,  G06F12/06

Abstract: A pointer circuit for pointing to elements in at least one collection of elements comprises a base pointer adapted to provide a first binary-coded value defining a first address of an element in the collection. The pointer circuit also comprises a binary shift circuit receiving the first binary-coded value provided by the base pointer and a second binary-coded value defining a shift value. The binary shift circuit combines the first and second binary-coded values to provide a third binary-coded value defining a second address of an element in the collection differing from the first address by the shift value. A shift value generator fed by the first binary-coded value generates the second binary-coded value depending on the first binary-coded value, in such a way that a generated shift value takes into account shift values corresponding to first binary-coded values preceding a current first binary-coded value in a prescribed first binary-coded value progression order. The pointer circuit can be expediently exploited for implementing redundancy in a memory.

Abstract translation: 用于指向至少一个元素集合中的元素的指针电路包括适于提供定义集合中的元素的第一地址的第一二进制编码值的基本指针。 指针电路还包括接收由基本指针提供的第一二进制编码值的二进制移位电路和定义移位值的第二二进制编码值。 二进制移位电路组合第一和第二二进制编码值以提供定义集合中的元素的第二地址的第三二进制编码值，该第一地址与第一地址不同，移位值不同。 由第一二进制编码值馈送的移位值生成器根据第一二进制编码值产生第二二进制编码值，使得所生成的移位值考虑到对应于先前的第一二进制编码值的移位值 在规定的第一二进制编码值进度顺序中的当前第一二进制编码值。 可以方便地利用指针电路来实现存储器中的冗余。

公开(公告)号：US20010014041A1

公开(公告)日：2001-08-16

申请号：US09767762

申请日：2001-01-23

Applicant: STMicroelectronics S.r.l

Inventor： Luigi Pascucci

IPC: G11C007/00

CPC classification number: H03K23/665 ,  G11C7/1018 ,  G11C8/04

Abstract: A memory counter circuit includes a plurality of mutually connected counter stages, an internal address bus interfaced with each one of the counter stages for sending an external address signal to each one of the counter stages, a circuit for loading the external address signal onto the internal address bus, and an enabling circuit for enabling a connection between the internal bus and each one of the counter stages. The enabling circuit may be driven by a true address latch enable signal. The memory counter circuit may further include a circuit for generating the true address latch enable signal starting from an external address latch signal and a fast address latch enable signal for driving the circuit for loading the external address signal onto the internal address bus. A signal generation circuit may also be included for generating clock signals for synchronizing each one of the counter stages. The synchronization signals are preferably not simultaneously active.

Abstract translation: 存储器计数器电路包括多个相互连接的计数器级，与每个计数器级相接口的内部地址总线，用于向每个计数器级发送外部地址信号，用于将外部地址信号加载到内部 地址总线，以及用于使能内部总线与每个计数器级之间的连接的使能电路。 使能电路可以由真实的地址锁存使能信号来驱动。 存储器计数器电路还可以包括用于从外部地址锁存信号开始产生真实地址锁存使能信号的电路和用于驱动用于将外部地址信号加载到内部地址总线上的电路的快速地址锁存使能信号。 还可以包括用于产生用于同步每个计数器级的时钟信号的信号发生电路。 同步信号优选地不是同时有效。

公开(公告)号：US20040062132A1

公开(公告)日：2004-04-01

申请号：US10616414

申请日：2003-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Luigi Pascucci

IPC: G11C008/02

CPC classification number: G11C8/12 ,  G11C16/08 ,  G11C16/16

Abstract: A line selector for a matrix of memory elements, for example a word line selector, comprises a plurality of line group selection circuits, each one allowing the selection of a respective group of matrix lines according to an address; each matrix line group includes at least one matrix line. Flag means are associated with each line group, that can be set to declare a pending status of a prescribed operation, for example an erase operation, for the respective matrix line group. Means are provided for entrusting the flag means with the selection of the respective line group during the execution of the prescribed operation, in alternative to the respective line group selection circuit. The flag means enable, when set, the execution of the prescribed operation on the respective matrix line group.

Abstract translation: 用于存储器元件矩阵的线选择器，例如字线选择器，包括多个线组选择电路，每个线组选择电路允许根据地址选择相应的矩阵线组; 每个矩阵线组包括至少一个矩阵线。 标志装置与每个线路组相关联，其可以被设置为声明对于各个矩阵线组的规定操作的挂起状态，例如擦除操作。 提供了用于在执行规定的操作期间委托标志装置选择相应的线路组的装置，以替代各个线路组选择电路。 标志意味着在设置时启用对各矩阵线组的规定操作的执行。

公开(公告)号：US20030119258A1

公开(公告)日：2003-06-26

申请号：US10294999

申请日：2002-11-14

Applicant: STMicroelectronics S.r.l.

Inventor： Luigi Pascucci

IPC: H01L021/336

CPC classification number: H01L27/11568 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: A process for fabricating a dual charge storage location, electrically programmable memory cell, comprising: forming a first dielectric layer over a semiconductor material layer of a first conductivity type; forming a charge trapping material layer over the first dielectric layer; selectively removing the charge trapping material layer from over a central channel region of the semiconductor material layer, thereby leaving two charge trapping material layer portions at sides of the central channel region; masking the central channel region and selectively implanting dopants of a second conductivity type into the semiconductor material layer to form memory cell source/drain regions at sides of the two charge trapping material layer portions; forming a second dielectric layer over the charge trapping material layer; and forming a polysilicon gate over the second dielectric layer, the polysilicon gate being superimposed over the central channel region and the two charge trapping material layer portions.

Abstract translation: 一种用于制造双电荷存储位置，电可编程存储单元的方法，包括：在第一导电类型的半导体材料层上形成第一介电层; 在所述第一介电层上形成电荷捕获材料层; 从半导体材料层的中心沟道区域上方选择性地去除电荷捕获材料层，从而在中心沟道区域的侧面留下两个电荷捕获材料层部分; 掩蔽中心沟道区并选择性地将第二导电类型的掺杂剂注入到半导体材料层中，以在两个电荷俘获材料层部分的侧面形成存储单元源极/漏极区; 在所述电荷俘获材料层上形成第二电介质层; 以及在所述第二电介质层上形成多晶硅栅极，所述多晶硅栅极叠加在所述中心沟道区域和所述两个电荷俘获材料层部分上。

公开(公告)号：US20040190335A1

公开(公告)日：2004-09-30

申请号：US10746555

申请日：2003-12-24

Applicant: STMicroelectronics S.r.l.

Inventor： Luigi Pascucci

IPC: G11C016/04 ,  G11C011/34

CPC classification number: G11C16/26 ,  G11C16/0475

Abstract: A semiconductor memory system comprising a memory matrix including a plurality of memory cells arranged in rows and columns and connected to a plurality of column lines, each memory cell of the same column having a first and a second terminal connected to a first and a second column line respectively. Furthermore, the memory system comprises a first and a second conduction line which can be connected to said first and second column lines, and generating means provided with at least a first and a second output line, making available a first and a second reading/writing voltage to said first and second terminal respectively. The memory system also comprises at least a first and a second selection transistor connected to the same command line and having corresponding operative terminals connected directly to the first and to the second output lines respectively and corresponding cell terminals connected directly to the first and to the second conduction lines respectively.

Abstract translation: 一种半导体存储器系统，包括存储矩阵，所述存储器矩阵包括以行和列排列并连接到多个列线的多个存储器单元，所述同一列的每个存储单元具有连接到第一和第二列的第一和第二端子 线。 此外，存储器系统包括可连接到所述第一和第二列线的第一和第二导线，以及设置有至少第一和第二输出线的发生装置，使第一和第二读/写 分别对所述第一和第二端子施加电压。 存储器系统还包括至少连接到相同命令行的第一和第二选择晶体管，并具有分别直接连接到第一和第二输出线的对应的操作终端，以及直接连接到第一和第二输出线的相应的单元终端 导线分别。

公开(公告)号：US20020067655A1

公开(公告)日：2002-06-06

申请号：US09972753

申请日：2001-10-05

Applicant: STMicroelectronics S.r.l.

Inventor： Luigi Pascucci

IPC: G11C008/00

CPC classification number: G11C16/26 ,  G11C7/1018 ,  G11C7/1045 ,  G11C16/32

Abstract: A timing and control structure for a memory, including the timing and control structure includes a first circuit that can recognize, on the basis of control signals supplied to the memory from the exterior, whether a random-access reading is to be executed, the control signals including a first control signal indicative of the presence of an address supplied to the memory from the exterior, and a second control signal that, upon switching edges of a first type, supplies to the control and timing structure a time base for the execution of the random-access readings and, upon switching edges of a second type, supplies a time base for the execution of the sequential readings, a second circuit controlled by the first circuit and upon a random-access reading, generates a first synchronism signal in response to a transition of the first type in the second control signal, a third circuit sensitive to transitions of the second type in the second control signal and which can generate a second synchronism signal upon transitions of the second type, and a fourth circuit controlled by the first circuit to supply a stimulus signal to a timing circuit of the memory, the stimulus signal corresponding to the first synchronism signal for a random-access reading, or to the second synchronism signal for a sequential reading.

Abstract translation: 包括定时和控制结构的存储器的定时和控制结构包括：第一电路，其可以基于从外部提供给存储器的控制信号来识别是否执行随机访问读取，控制 包括指示从外部提供给存储器的地址的存在的第一控制信号的信号以及在第一类型的切换边缘向控制和定时结构提供执行时间的时间的第二控制信号 随机访问读数，并且在第二类型的切换边缘提供用于执行顺序读数的时基，由第一电路控制的第二电路和随机访问读取产生响应中的第一同步信号 到第二控制信号中的第一类型的转变，第三电路对第二控制信号中的第二类型的转变敏感，并且可以产生第二个s 以及由第一电路控制的第四电路，以将激励信号提供给存储器的定时电路，对应于用于随机存取读取的第一同步信号的激励信号，或者对于第 用于顺序读取的第二同步信号。

公开(公告)号：US20020054537A1

公开(公告)日：2002-05-09

申请号：US09974737

申请日：2001-10-09

Applicant: STMicroelectronics S.r.l.

Inventor： Luigi Pascucci

IPC: G11C008/00

CPC classification number: G11C8/04

Abstract: An internal addressing structure for a semiconductor memory with at least two memory banks, includes a counter associated for operation with each memory bank and capable of generating sequences of digital codes for addressing locations in the corresponding bank, a first circuit for causing a selective updating of the counters, a second circuit for loading into the counters a common initial digital code, forming part of an initial address supplied to the memory from the outside through an addressing line bus, corresponding to an initial memory location, and a third circuit capable of detecting a first signal, supplied to the memory from the outside and indicating the presence of a digital code on the bus, to cause the common initial digital code to be loaded into the counters. The first circuit means iscapable of identifying, on the basis of the initial address, the bank to which the initial memory location belongs, and of consequently causing the periodic updating of the counters in a sequence which depends on the bank to which the initial memory location belongs, in such a way that successive memory locations preceding or following the initial location are addressed in sequence, each of these successive locations belonging to a corresponding memory bank, according to an interlaced system.

Abstract translation: 一种用于具有至少两个存储体的半导体存储器的内部寻址结构，包括与每个存储体一起操作的计数器，并且能够产生用于寻址相应存储单元中的位置的数字代码序列;第一电路， 计数器，用于将对应于初始存储器位置的公共初始数字代码加载到计数器中的第二电路，形成从外部通过寻址线总线提供给存储器的初始地址的一部分，以及能够检测的第三电路 从外部提供给存储器并指示总线上存在数字代码的第一信号，以使公共初始数字代码被加载到计数器中。 第一电路装置能够基于初始地址识别初始存储器位置所属的存储体，并且因此导致依赖于初始存储器位置的存储体的序列中的计数器的周期性更新 属于这样一种方式，使得在初始位置之前或之后的连续存储器位置被依次寻址，这些连续位置中的每一个属于对应的存储体，根据隔行扫描系统。