公开(公告)号：US20040012009A1

公开(公告)日：2004-01-22

申请号：US10371154

申请日：2003-02-20

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

IPC: H01L047/00 ,  H01L021/76

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

Abstract translation: 电子半导体器件具有在第一导电区域和第二导电区域之间的亚光刻接触面积。 第一导电区域是杯状的并且具有垂直壁，其在顶部平面图中沿着细长形状的封闭线延伸。 第一导电区域的一个壁形成第一薄部分并且具有在第一方向上的第一尺寸。 第二导电区域具有第二薄部分，该第二薄部分具有横向于第一尺寸的第二方向的第二亚光刻尺寸。 第一和第二导电区域在其薄部分处直接电接触并形成亚光刻接触区域。 细长形状选择在第一方向上伸长的矩形和椭圆形之间。 因此，即使在限定导电区域的掩模之间存在小的不对准的情况下，接触区域的尺寸也保持近似恒定。

公开(公告)号：US20030219924A1

公开(公告)日：2003-11-27

申请号：US10313991

申请日：2002-12-05

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Roberto Bez ,  Fabio Pellizzer ,  Caterina Riva ,  Romina Zonca

IPC: H01L021/06 ,  H01L021/4763

CPC classification number: G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691 ,  Y10S438/947

Abstract: A contact structure, including a first conducting region having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region having a second thin portion with a second sublithographic dimension in a second direction transverse to said first direction; the first and second thin portions being in direct electrical contact and defining a contact area having a sublithographic extension. The thin portions are obtained using deposition instead of lithography: the first thin portion is deposed on a wall of an opening in a first dielectric layer; the second thin portion is obtained by deposing a sacrificial region on vertical wall of a first delimitation layer, deposing a second delimitation layer on the free side of the sacrificial region, removing the sacrificial region to form a sublithographic opening that is used to etch a mold opening in a mold layer and filling the mold opening.

Abstract translation: 一种接触结构，包括：第一导电区域，具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 第二导电区域，具有第二薄部分，具有横向于所述第一方向的第二方向的第二亚光刻尺寸; 第一和第二薄部分直接电接触并且限定具有亚光刻延伸部的接触区域。 使用沉积代替光刻获得薄部分：第一薄部分被放置在第一介电层中的开口的壁上; 通过在第一限定层的垂直壁上去除牺牲区域，在牺牲区域的自由侧上取代第二限定层，去除牺牲区域以形成用于蚀刻模具的亚光刻开口来获得第二薄部分 在模具层中开口并填充模具开口。

公开(公告)号：US20040150093A1

公开(公告)日：2004-08-05

申请号：US10680727

申请日：2003-10-07

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

IPC: H01L023/48

CPC classification number: H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

Abstract: A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

Abstract translation: 单元阵列由多个单元形成，每个单元包括选择双极晶体管和存储组件。 电池阵列形成在包括P型共用集电极区域的主体中; 多个N型基极区，覆盖在公共集电极区域上; 在基区中形成多个P型发射极区; 以及形成在所述基极区域中的多个N型基极接触区域和比所述基极区域更高的掺杂水平的基极接触区域，其中每个基极区域由至少两个相邻的双极晶体管共享。

公开(公告)号：US20030231530A1

公开(公告)日：2003-12-18

申请号：US10372761

申请日：2003-02-20

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

IPC: G11C029/00

CPC classification number: H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: The phase change memory cell is formed by a resistive element and by a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

Abstract translation: 相变存储单元由电阻元件和相变材料的存储区形成。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区域具有第二薄部分，所述第二薄部分具有横向于所述第一尺寸的第二方向的第二亚光刻尺寸。 第一薄部分和第二薄部分直接电接触并限定亚光刻延伸部分的接触面积。 第二薄部分被由限定光刻开口的模具层围绕的氧化物间隔部分侧向限定。 通过间隔物形成技术在形成光刻开口之后形成间隔部分。

公开(公告)号：US20040214415A1

公开(公告)日：2004-10-28

申请号：US10758289

申请日：2004-01-15

Applicant: STMicroelectronics S.r.I. ,  OVONYX Inc.

Inventor： Fabio Pellizzer ,  Roberto Bez ,  Marina Tosi

IPC: H01L021/28

CPC classification number: H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A process wherein an insulating region is formed in a body at least around an array portion of a semiconductor body; a gate electrode of semiconductor material is formed on top of a circuitry portion of the semiconductor body; a first silicide protection mask is formed on top of the array portion; the gate electrode and the active areas of the circuitry portion are silicided and the first silicide protection mask is removed. The first silicide protection mask (is of polysilicon and is formed simultaneously with the gate electrode. A second silicide protection mask of dielectric material covering the first silicide protection mask is formed before silicidation of the gate electrode. The second silicide protection mask is formed simultaneously with spacers formed laterally to the gate electrode.

Abstract translation: 一种绝缘区域至少在半导体本体的阵列部分周围形成在主体中的工艺; 半导体材料的栅电极形成在半导体本体的电路部分的顶部; 在阵列部分的顶部形成第一硅化物保护掩模; 栅电极和电路部分的有源区被硅化，并且去除第一硅化物保护掩模。 第一硅化物保护掩模（多晶硅，并与栅电极同时形成）在栅极电极硅化之前形成覆盖第一硅化物保护掩模的第二硅化物保护掩模，第二硅化物保护掩膜与 间隔件横向形成到栅电极。

公开(公告)号：US20040173869A1

公开(公告)日：2004-09-09

申请号：US10713538

申请日：2003-11-14

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto Bez ,  Alessandro Grossi

IPC: H01L029/00

CPC classification number: H01L21/76232 ,  H01L21/76229 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11531

Abstract: A process for self-aligned manufacturing of integrated electronic devices includes: forming, in a semiconductor wafer having a substrate, insulation structures that delimit active areas and project from the substrate; forming a first conductive layer, which coats the insulation structures and the active areas; and partially removing the first conductive layer. In addition, recesses are formed in the insulation structures before forming said first conductive layer.

Abstract translation: 一种用于集成电子器件的自对准制造的方法包括：在具有衬底的半导体晶片中形成限定有源区并从衬底突出的绝缘结构; 形成第一导电层，其涂覆绝缘结构和有源区; 并部分地去除第一导电层。 此外，在形成所述第一导电层之前，在绝缘结构中形成凹部。

公开(公告)号：US20030096477A1

公开(公告)日：2003-05-22

申请号：US10337556

申请日：2003-01-07

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto Bez ,  Emilio Camerlenghi ,  Stefano Ratti

IPC: H01L021/336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.

公开(公告)号：US20020033499A1

公开(公告)日：2002-03-21

申请号：US09919341

申请日：2001-07-30

Applicant: STMicroelectronics S.r.l.

Inventor： David Esseni ,  Luca Selmi ,  Roberto Bez ,  Alberto Modelli

IPC: H01L029/788

CPC classification number: H01L29/66825 ,  G11C16/0416 ,  H01L27/11521 ,  H01L29/7885

Abstract: The memory cell is formed in a body of a P-type semiconductor material forming a channel region and housing N-type drain and source regions at two opposite sides of the channel region. A floating gate region extends above the channel region. A P-type charge injection region extends in the body contiguously to the drain region, at least in part between the channel region and the drain region. An N-type base region extends between the drain region, the charge injection region, and the channel region. The charge injection region and the drain region are biased by special contact regions so as to forward bias the PN junction formed by the charge injection region and the base region. The holes thus generated in the charge injection region are directly injected through the base region into the body, where they generate, by impact, electrons that are injected towards the floating gate region.

Abstract translation: 存储单元形成在形成沟道区域的P型半导体材料的主体中，并且在沟道区域的两个相对侧容纳N型漏极和源极区域。 浮动栅极区域在沟道区域的上方延伸。 P型电荷注入区域至少部分地在沟道区域和漏极区域之间在体内连续地延伸到漏极区域。 N型基极区域在漏极区域，电荷注入区域和沟道区域之间延伸。 电荷注入区域和漏极区域被特殊的接触区域偏置，以使由电荷注入区域和基极区域形成的PN结正向偏置。 这样在电荷注入区域中产生的孔直接通过基底区域注入到体内，在那里它们通过冲击产生被注入到浮动栅极区域的电子。

公开(公告)号：US20020025631A1

公开(公告)日：2002-02-28

申请号：US09900501

申请日：2001-07-06

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto Bez ,  Emilio Camerlenghi ,  Stefano Ratti

IPC: H01L021/336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.

Abstract translation: 用于在半导体衬底上制造非易失性存储单元的工艺包括由氧化物层形成由与衬底隔离的第一多晶硅层组成的堆叠结构。 级联蚀刻第一多晶硅层，氧化物层和半导体衬底以限定电池的浮动栅极区域的第一部分和与存储器单元的有效区域接合的至少一个沟槽。 至少一个沟槽填充有隔离层。 该方法还包括在半导体的整个暴露表面上沉积第二多晶硅层，以及蚀刻第二多晶硅层以暴露形成在第一多晶硅层中的浮栅区域，从而形成与第一多晶硅层的上述部分相邻的延伸。