公开(公告)号：US20240274173A1

公开(公告)日：2024-08-15

申请号：US18498267

申请日：2023-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheolhui LEE ,  Youngmin JO ,  Anil KAVALA ,  Jungjune PARK ,  Chiweon YOON

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/14

CPC classification number: G11C7/222 ,  G11C7/1081 ,  G11C7/14 ,  G11C7/225

Abstract: Provided is a nonvolatile memory including a receive buffer configured to generate a buffer signal by comparing an input signal with a reference voltage, a reference voltage calibrator configured to generate a calibrated reference voltage code signal based on a reference voltage code signal and the buffer signal, and a reference voltage generator configured to generate a reference voltage corresponding to the calibrated reference voltage code signal. In addition, the read reference voltage calibrator includes a duty cycle monitor configured to generate a monitoring signal by measuring a duty cycle of the buffer signal, an up/down counter configured to generate a count number signal by comparing a reference duty cycle with a measurement duty cycle corresponding to the monitoring signal, and a code calculator configured to generate the calibrated reference voltage code signal based on the count number signal and the reference voltage code signal.

公开(公告)号：US20240257848A1

公开(公告)日：2024-08-01

申请号：US18494258

申请日：2023-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwanseok KU ,  Youngmin JO ,  Anil KAVALA ,  Jungjune PARK ,  Chiweon YOON

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C8/18

Abstract: A memory package includes a data input/output pin, a data strobe pin, a plurality of memory devices, and a buffer device. The data input/output pin receives a data signal. The data strobe pin receives a data strobe signal. The plurality of memory devices operate based on the data signal and the data strobe signal. The buffer device is between the data input/output pin, the data strobe pin and the plurality of memory devices, and performs a training operation based on training data and the data strobe signal in response to the data signal including the training data and the data strobe signal being received. During the training operation, the buffer device sets different delays on a plurality of sub-training data included in the training data, and the sub-training data on which the different delays are set are stored in different memory regions of the plurality of memory devices.

公开(公告)号：US20240321330A1

公开(公告)日：2024-09-26

申请号：US18611213

申请日：2024-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Anil KAVALA ,  Youngmin Jo ,  Jungjune Park ,  Chiweon Yoon

IPC: G11C7/22 ,  G11C7/14 ,  H03L7/099

CPC classification number: G11C7/222 ,  G11C7/14 ,  H03L7/0998

Abstract: A storage device includes a buffer chip and a memory device. The memory device transmits a random data signal and a data strobe signal to the buffer chip based on a clock signal received from the buffer chip. The buffer chip includes a delay circuit that delays the data strobe signal by a delay time to generate a delayed data strobe signal, a sampler that receives the delayed data strobe signal from the delay circuit and samples the random data signal based on the delayed data strobe signal to generate sampled data, a comparator that compares internal data with the sampled data to generate a comparison result, and a counter module that receives the comparison result from the comparator and determines a target delay based on the comparison result. The buffer chip delays the delayed data strobe signal based on the target delay.

公开(公告)号：US20190158109A1

公开(公告)日：2019-05-23

申请号：US16191367

申请日：2018-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anil KAVALA ,  Seon-kyoo LEE ,  Byung-hoon JEONG ,  Jeong-don IHM ,  Young-don CHOI

IPC: H03M1/78 ,  G11C5/14 ,  G05F3/08

CPC classification number: H03M1/785 ,  G05F3/08 ,  G11C5/147 ,  G11C7/14

Abstract: A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.

公开(公告)号：US20170048087A1

公开(公告)日：2017-02-16

申请号：US15099987

申请日：2016-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEON-KYOO LEE ,  Jeong-Don IHM ,  Anil KAVALA ,  Byung-Hoon JEONG

IPC: H04L25/03

CPC classification number: H04L25/03019 ,  H04L25/03114 ,  H04L27/01 ,  H04L2025/03535

Abstract: An equalizer circuit may include an equalizer controller and a plurality of equalizers. The equalizer controller may prove separate sets of enable signals, delay control signals and voltage control signals to the separate equalizers based on a control signal. The equalizers provide equalizer signals to separate connection nodes between separate pairs of logic circuits. An equalizer may be selectively activated based on a received enable signal. An equalizer may include a delay control circuit and a voltage control circuit. The delay control circuit may delay a received transfer signal to generate a delayed transfer signal based on a received delay control signal. The voltage control circuit may generate an equalizer signal based on the delayed transfer signal and a received voltage control signal. The equalizer circuit may reduce inter-symbol interference in the integrated circuit based on providing the equalizer signals to the connection nodes between the logic circuits.

Abstract translation: 均衡器电路可以包括均衡器控制器和多个均衡器。 均衡器控制器可以基于控制信号向单独的均衡器证明单独的使能信号组，延迟控制信号和电压控制信号。 均衡器提供均衡器信号以在单独的逻辑电路对之间分离连接节点。 可以基于接收到的使能信号来选择性地激活均衡器。 均衡器可以包括延迟控制电路和电压控制电路。 延迟控制电路可以延迟接收到的传送信号，以基于接收的延迟控制信号产生延迟的传送信号。 电压控制电路可以基于延迟的传送信号和接收的电压控制信号产生均衡器信号。 均衡器电路可以通过将均衡器信号提供给逻辑电路之间的连接节点来减小集成电路中的符号间干扰。