公开(公告)号：US11908855B2

公开(公告)日：2024-02-20

申请号：US17880819

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonah Nam ,  Byungju Kang ,  Byungsung Kim ,  Hyelim Kim ,  Sungho Park ,  Yubo Qian

IPC: H01L27/088 ,  H01L23/538 ,  H01L29/06 ,  H01L29/423 ,  B82Y10/00 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/02 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L23/5384 ,  H01L29/0653 ,  H01L29/4232

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US20240128354A1

公开(公告)日：2024-04-18

申请号：US18231549

申请日：2023-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo Park ,  Byungju Kang ,  Junghan Lee ,  Jaehyoung Lim

IPC: H01L29/66 ,  H01L23/48

CPC classification number: H01L29/66545 ,  H01L23/481 ,  H01L29/66795

Abstract: In a method of manufacturing a semiconductor device, an alignment key is formed through a portion of a substrate including first and second surfaces opposite to each other, which is adjacent to the second surface of the substrate. A transistor including a gate structure and a source/drain layer is formed on the second surface of the substrate. A portion of the substrate adjacent to the first surface of the substrate is removed to expose the alignment key. A contact plug is formed through a portion of the substrate adjacent to the first surface of the substrate to be electrically connected to the source/drain layer. A power rail is formed on the first surface of the substrate to be electrically connected to the contact plug.

公开(公告)号：US11410994B2

公开(公告)日：2022-08-09

申请号：US17024044

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonah Nam ,  Byungju Kang ,  Byungsung Kim ,  Hyelim Kim ,  Sungho Park ,  Yubo Qian

IPC: H01L27/088 ,  H01L23/538 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/02 ,  H01L29/775 ,  H01L29/78

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US10211089B2

公开(公告)日：2019-02-19

申请号：US15619648

申请日：2017-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moon Gi Cho ,  Byungju Kang ,  Janie Hyojin Kim

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L21/02

Abstract: A semiconductor device and a fabricating method thereof are provided. The method includes sequentially forming an interlayer insulating layer and a hard mask layer on a substrate with first and second regions, performing a first patterning process on the hard mask layer to form first openings in the first and second regions, performing a second patterning process on the hard mask layer to form second openings in the first and second regions, and performing a third patterning process on the hard mask layer to selectively form at least one third opening in only the second region. The third patterning process includes forming a first photoresist pattern with openings on the hard mask layer, and the opening of the first photoresist pattern on the first region is overlapped with the second opening on the first region, when viewed in a plan view.

公开(公告)号：US20230378027A1

公开(公告)日：2023-11-23

申请号：US18113133

申请日：2023-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhyeong CHOI ,  Jiwook Kwon ,  Byungju Kang ,  Chulhong Park ,  Kwanyoung Chun

IPC: H01L23/48 ,  H01L23/522

CPC classification number: H01L23/481 ,  H01L23/5226

Abstract: A semiconductor device includes: a semiconductor substrate having power arrangement regions; a first interconnection structure disposed on the semiconductor substrate and including first interconnection patterns and power lines; a second interconnection structure disposed on the semiconductor substrate and including second interconnection patterns; and through-electrodes passing through each of the power arrangement regions and contacting the power lines, wherein the first interconnection patterns include first interconnection lines, wherein the power lines are disposed on a same height level as a first interconnection line, among the first interconnection lines, and are parallel to each other, wherein the power arrangement regions are parallel to each other, and wherein intersection regions, in which the power arrangement regions and the power lines intersect, include a plurality of first active intersection regions, one dummy intersection region, and a plurality of second active intersection regions, sequentially arranged.

公开(公告)号：US11804480B2

公开(公告)日：2023-10-31

申请号：US17527432

申请日：2021-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Panjae Park ,  Byungju Kang ,  Yoonjeong Kim ,  Kwanyoung Chun

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/786 ,  H01L23/528 ,  B82Y10/00

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0847 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: An integrated circuit chip including a substrate including first and second element regions; a first channel active region extending in a first direction; a second channel active region; gate lines extending in a second direction and intersecting the first and second channel active regions; a diffusion break extending in the second direction; source/drain regions at opposite sides of the gate lines and on the first and second channel active regions; a first power line electrically connected to the source/drain regions; and a second power line electrically connected to the source/drain regions and having a lower voltage level than the first power line, wherein the diffusion break includes a first region including an insulator and overlapping the first element region, and a second region including a same material as the gate lines and overlapping the second element region, wherein the second region is electrically connected to the second power line.

公开(公告)号：US12261171B2

公开(公告)日：2025-03-25

申请号：US18416375

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonah Nam ,  Byungju Kang ,  Byungsung Kim ,  Hyelim Kim ,  Sungho Park ,  Yubo Qian

IPC: H01L27/088 ,  B82Y10/00 ,  H01L21/8234 ,  H01L23/538 ,  H01L27/02 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US20230068716A1

公开(公告)日：2023-03-02

申请号：US17751093

申请日：2022-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungju Kang ,  Raheel Azmat ,  Jiwook Kwon ,  Suhyeon Kim ,  Kwanyoung Chun

IPC: H01L27/02 ,  G06F30/392 ,  G06F30/394 ,  H01L23/528 ,  H01L23/522 ,  H01L27/118

Abstract: A semiconductor device includes: a standard cell including a plurality of active patterns extending in a first direction, a gate structure intersecting the plurality of active patterns and extending in a second direction, and source/drain regions respectively provided on the plurality of active patterns positioned on both sides of the gate structure; a plurality of signal lines extending on the standard cell in the first direction, arranged in the second direction, and electrically connected to the standard cell; and first and second power straps extending on the standard cell in the first direction, electrically connected to some of the source/drain regions, and supplying power to the standard cell, wherein each of the first and second power straps is provided on the standard cell while provided on the same line as any one of the plurality of signal lines in the first direction.