公开(公告)号：US09786675B2

公开(公告)日：2017-10-10

申请号：US15043640

申请日：2016-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehun Jung ,  Zhiliang Xia ,  Daewoong Kang ,  Dae Sin Kim ,  Kwang Soo Seol ,  Homin Son ,  Seunghyun Lim

IPC: H01L29/788 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792 ,  H01L29/7923

Abstract: A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes. An energy band gap of the first charge storage layer is smaller than those of the second and third charge storage layers. The first charge storage layer is thicker than the second and third charge storage layers.

公开(公告)号：US10998330B2

公开(公告)日：2021-05-04

申请号：US15476044

申请日：2017-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunmog Park ,  Daewoong Kang ,  Chadong Yeo ,  Jaehoon Jang ,  Joongshik Shin

IPC: H01L29/04 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/16 ,  H01L29/49 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157

Abstract: A {111} plane of a substrate having a silicon crystal structure meets a top surface of the substrate to form an interconnection line on the top surface. A first stacked structure and a second stacked structure is formed on the substrate. Each of the first and the second stacked structures includes gate electrodes stacked on the substrate. A transistor is disposed on the substrate and positioned between the first stacked structure and the second stacked structure. The transistor includes a gate electrode extending in a first direction, a source region and a drain region. The source and the drain regions are disposed at both sides of the gate electrode in a second direction crossing the first direction. The interconnection line is extended at an angle with respect to the second direction.

公开(公告)号：US09741735B2

公开(公告)日：2017-08-22

申请号：US14993485

申请日：2016-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Wook Lee ,  Daewoong Kang ,  Dae Sin Kim ,  Kwang Soo Seol ,  Homin Son ,  Seunghyun Lim

IPC: H01L27/115 ,  H01L29/423 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/4234 ,  H01L29/42348

Abstract: A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating patterns, an active pillar passing through the stack and electrically connected to the substrate and a charge storing layer interposed between the stack and the active pillar. The charge storing layer includes a first portion between the active pillar and one of the gate patterns, a second portion between the active pillar and one of the insulating patterns, and a third portion joining the first portion to the second portion and having a thickness less than that of the first portion.

公开(公告)号：US09831265B2

公开(公告)日：2017-11-28

申请号：US15165135

申请日：2016-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nambin Kim ,  Daewoong Kang ,  Dae Sin Kim ,  Kwang Soo Seol ,  Homin Son ,  Changsub Lee ,  Seunghyun Lim ,  Sunghoi Hur

IPC: H01L23/48 ,  H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: Provided is a semiconductor device including a substrate, gate electrodes vertically stacked on the substrate, insulating patterns between the gate electrodes, an active pillar provided to penetrate the gate electrodes and the insulating patterns and electrically coupled with the substrate, and a memory pattern provided between the gate electrodes and the active pillar and between the insulating patterns and the active pillar. The gate electrodes include edge portions extending between the memory pattern and the insulating patterns.

公开(公告)号：US08809146B2

公开(公告)日：2014-08-19

申请号：US13751679

申请日：2013-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daewoong Kang ,  Sungnam Chang ,  JinJoo Kim ,  Kyongjoo Lee ,  Eun-Jung Lee

IPC: H01L21/336

CPC classification number: H01L21/76 ,  H01L21/764 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: Methods for forming semiconductor memory structures including a gap between adjacent gate structures are provided. The methods may include forming an insulation layer between the adjacent gate structures. In some embodiments, the methods may include subsequently removing a portion of the insulation layer to leave the gap between the adjacent gate structures.

Abstract translation: 提供了用于形成包括相邻栅极结构之间的间隙的半导体存储器结构的方法。 所述方法可以包括在相邻栅极结构之间形成绝缘层。 在一些实施例中，所述方法可以包括随后去除绝缘层的一部分以留下相邻栅极结构之间的间隙。