公开(公告)号：US12183402B2

公开(公告)日：2024-12-31

申请号：US18063912

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Ho Seo ,  Yong-Wan Son ,  Dogyeong Lee ,  Youngha Choi

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34

Abstract: Disclosed is an operation method of a memory device that includes a memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate. The plurality of cell transistors may include a ground selection transistor and an erase control transistor. The erase control transistor may be between the substrate and the ground selection transistor. The operation method may include performing a first erase operation on the ground selection transistor, performing a first program operation on the erase control transistor after the first erase operation, performing a second program operation on the ground selection transistor after the first program operation, and performing a second erase operation on the erase control transistor after the second program operation.

公开(公告)号：US12068047B2

公开(公告)日：2024-08-20

申请号：US17535771

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukeun Kang ,  Junho Seo ,  Dogyeong Lee ,  Juwon Lee

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/28

CPC classification number: G11C16/3495 ,  G11C16/08 ,  G11C16/102 ,  G11C16/14 ,  G11C16/28

Abstract: An operating method of a memory system includes storing normal data to a first storage area of a non-volatile memory in a first program mode among multiple program modes defined according to a number of bits stored in each memory cell; storing dummy data in the first storage area in at least one of the multiple program modes including the first program mode; and copying the normal data from the first storage area to a second storage area of the non-volatile memory based on dummy data stored in the first program mode.

公开(公告)号：US12020759B2

公开(公告)日：2024-06-25

申请号：US17878019

申请日：2022-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Ho Seo ,  Juwon Lee ,  Suk-Eun Kang ,  Dogyeong Lee ,  Youngwook Jeong ,  Sang-Hyun Joo

IPC: G11C16/34 ,  G06N3/08 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

CPC classification number: G11C16/3459 ,  G06N3/08 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/3495

Abstract: An operation method of a nonvolatile memory device includes performing a 1-stage program step and a 1-stage verify step on a first word line, storing a first time stamp, performing the 1-stage program step and the 1-stage verify step on a second word line, storing a second time stamp, calculating a delay time based on the first time stamp and the second time stamp, determining whether the delay time is greater than a threshold value, adjusting at least one 2-stage verify voltage associated with the first word line from a first voltage level to a second voltage level based on the delay time, and performing a 2-stage program step and a 2-stage verify step on the first word line. A level of the at least one 1-stage verify voltage is lower than the second voltage level, and the second voltage level is lower than the first voltage level.