公开(公告)号：US09318700B2

公开(公告)日：2016-04-19

申请号：US14740929

申请日：2015-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Zhe Wu ,  Jeong-Hee Park ,  Dong-Ho Ahn ,  Jung-Hwan Park ,  Jun-Ku Ahn ,  Sung-Lae Cho ,  Hideki Horii

IPC: H01L21/20 ,  H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1666 ,  H01L45/1683

Abstract: In a method of manufacturing a phase change memory device, an insulating interlayer having a through opening is formed on a substrate, at least one conformal phase change material layer pattern is formed along the sides of the opening, and a plug-like phase change material pattern having a composition different from that of each conformal phase change material layer pattern is formed on the at least one conformal phase change material layer pattern as occupying a remaining portion of the opening. Energy is applied to the phase change material layer patterns to form a mixed phase change material layer pattern including elements from the conformal and plug-like phase change material layer patterns.

Abstract translation: 在相变存储装置的制造方法中，在基板上形成具有通孔的绝缘中间层，沿开口侧形成至少一个共形相变材料层图案，并且形成插塞状相变材料 具有不同于每个共形相变材料层图案的组成的图案形成在占据开口的剩余部分的至少一个共形相变材料层图案上。 将能量施加到相变材料层图案以形成包括来自保形和插塞状相变材料层图案的元件的混合相变材料层图案。

公开(公告)号：US10236444B2

公开(公告)日：2019-03-19

申请号：US15432346

申请日：2017-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hideki Horii ,  Seong-Geon Park ,  Dong-Ho Ahn ,  Jung-Moo Lee

IPC: H01L45/00 ,  H01L27/24

Abstract: A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.

公开(公告)号：US10388867B2

公开(公告)日：2019-08-20

申请号：US15294873

申请日：2016-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Zhe Wu ,  Soon-Oh Park ,  Jeong-Hee Park ,  Dong-Ho Ahn ,  Hideki Horii

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

Abstract: A variable resistance memory device including a selection pattern; an intermediate electrode contacting a first surface of the selection pattern; a variable resistance pattern on an opposite side of the intermediate electrode relative to the selection pattern; and a first electrode contacting a second surface of the selection pattern and including a n-type semiconductor material, the second surface of the selection pattern being opposite the first surface thereof.

公开(公告)号：US20190189920A1

公开(公告)日：2019-06-20

申请号：US16277491

申请日：2019-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hideki Horii ,  Seong-Geon Park ,  Dong-Ho Ahn ,  Jung-Moo Lee

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1683 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144

Abstract: A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.

公开(公告)号：US20160102396A1

公开(公告)日：2016-04-14

申请号：US14876183

申请日：2015-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zhe Wu ,  Jung-Hwan Park ,  Jeong-Hee Park ,  Dong-Ho Ahn

IPC: C23C14/54 ,  C23C14/14 ,  C23C14/50 ,  C23C14/22

CPC classification number: C23C14/541 ,  C23C14/0623 ,  C23C14/50 ,  C23C14/542 ,  C23C14/548 ,  H01J37/32522 ,  H01J37/32623 ,  H01J37/32724 ,  H01J37/34

Abstract: A physical vapor deposition (PVD) apparatus for forming a phase-changeable layer includes a process chamber including a loading chamber configured to load a substrate, and a depositing chamber configured to deposit ion particles of a phase-changeable material onto the substrate; a target member on an upper portion of the depositing chamber and configured to provide the ion particles of the phase-changeable material which react with process gases in a plasma state; a plasma generator configured to generate a process gas plasma from the process gases; a chuck on a lower portion of the depositing chamber and holding the substrate, the chuck including a heater configured to heat the substrate, and at least one electrode configured to guide the ion particles of the phase-changeable material to the substrate; and a supplementary heater in the process chamber and configured to transfer radiant heat around the substrate.

Abstract translation: 用于形成相变层的物理气相沉积（PVD）装置包括处理室，该处理室包括被配置为加载基板的装载室和被配置成将相变材料的离子颗粒沉积到基板上的沉积室; 沉积室上部的目标构件，其构造成提供与等离子体状态的处理气体反应的相变材料的离子颗粒; 等离子体发生器，其被配置为从所述处理气体产生处理气体等离子体; 卡盘位于沉积室的下部并保持基板，卡盘包括构造成加热基板的加热器和至少一个电极，其被配置为将相变材料的离子颗粒引导到基板; 以及处理室中的附加加热器，并且被配置为在衬底周围传递辐射热。