-
1.发明授权Methods of forming a thin layer and methods of manufacturing a phase change memory device using the same 有权形成薄层的方法和使用其制造相变存储器件的方法公开(公告)号：US08993441B2
公开(公告)日：2015-03-31
申请号：US14189053
申请日：2014-02-25
发明人： Do-Hyung Kim , Eun-Tae Kim , Sung-Lae Cho
CPC分类号： H01L45/1616 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
摘要： A method of forming a thin layer and a method of manufacturing a phase change memory device, the method of forming a thin layer including providing a first deposition source onto a substrate, the first deposition source not including tellurium; and providing a second deposition source onto the substrate, the second deposition source including a first tellurium precursor represented by the following Formula 1 and a second tellurium precursor represented by following the Formula 2: Te(CH(CH3)2)2 Formula 1 Ten(CH(CH3)2)2 Formula 2 wherein, in Formula 2, n is an integer greater than or equal to 2.
摘要翻译： 一种形成薄层的方法和制造相变存储器件的方法，所述形成薄层的方法包括在基底上提供第一沉积源，所述第一沉积源不包括碲; 并且在所述衬底上提供第二沉积源，所述第二沉积源包括由下式1表示的第一碲前体和由下式2表示的第二碲前体：Te（CH（CH 3）2）2式1 10 CH（CH 3）2）2式2其中，在式2中，n是大于或等于2的整数。
-
公开(公告)号：US20130302966A1
公开(公告)日：2013-11-14
申请号：US13942149
申请日：2013-07-15
发明人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
IPC分类号： H01L45/00
CPC分类号： H01L45/1683 , H01L27/2463 , H01L45/06
摘要： A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
摘要翻译： 形成基板上的导电图案。 形成具有露出导电图案的开口的绝缘层。 底部电极形成在导电图案和开口的第一侧壁上。 在底部电极和开口的第二侧壁上形成间隔物。 间隔件和底部电极形成为低于绝缘层的顶表面。 数据存储插头形成在底部电极和间隔件上。 数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。 在数据存储插头上形成位线。
-
公开(公告)号：US09318700B2
公开(公告)日：2016-04-19
申请号：US14740929
申请日：2015-06-16
发明人： Zhe Wu , Jeong-Hee Park , Dong-Ho Ahn , Jung-Hwan Park , Jun-Ku Ahn , Sung-Lae Cho , Hideki Horii
CPC分类号： H01L45/06 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/1253 , H01L45/141 , H01L45/144 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/1666 , H01L45/1683
摘要： In a method of manufacturing a phase change memory device, an insulating interlayer having a through opening is formed on a substrate, at least one conformal phase change material layer pattern is formed along the sides of the opening, and a plug-like phase change material pattern having a composition different from that of each conformal phase change material layer pattern is formed on the at least one conformal phase change material layer pattern as occupying a remaining portion of the opening. Energy is applied to the phase change material layer patterns to form a mixed phase change material layer pattern including elements from the conformal and plug-like phase change material layer patterns.
摘要翻译： 在相变存储装置的制造方法中，在基板上形成具有通孔的绝缘中间层，沿开口侧形成至少一个共形相变材料层图案，并且形成插塞状相变材料 具有不同于每个共形相变材料层图案的组成的图案形成在占据开口的剩余部分的至少一个共形相变材料层图案上。 将能量施加到相变材料层图案以形成包括来自保形和插塞状相变材料层图案的元件的混合相变材料层图案。
-
公开(公告)号：US08790976B2
公开(公告)日：2014-07-29
申请号：US13942149
申请日：2013-07-15
发明人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
IPC分类号： H01L21/336
CPC分类号： H01L45/1683 , H01L27/2463 , H01L45/06
摘要： A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
摘要翻译： 形成基板上的导电图案。 形成具有露出导电图案的开口的绝缘层。 底部电极形成在导电图案和开口的第一侧壁上。 在底部电极和开口的第二侧壁上形成间隔物。 间隔件和底部电极形成为低于绝缘层的顶表面。 数据存储插头形成在底部电极和间隔件上。 数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。 在数据存储插头上形成位线。
-
公开(公告)号：US08834968B2
公开(公告)日：2014-09-16
申请号：US13708914
申请日：2012-12-07
发明人： Byoung-Jae Bae , Sung-Lae Cho , Jin-Il Lee , Hye-Young Park , Do-Hyung Kim
CPC分类号： C01B19/04 , C23C16/305 , C23C16/45531 , C23C16/45553 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/1683 , H01L45/1691
摘要： In one aspect, a method of forming a phase change material layer is provided. The method includes supplying a reaction gas including the composition of Formula 1 into a reaction chamber, supplying a first source which includes Ge(II) into the reaction chamber, and supplying a second source into the reaction chamber. Formula 1 is NR1R2R3, where R1, R2 and R3 are each independently at least one selected from the group consisting of H, CH3, C2H5, C3H7, C4H9, Si(CH3)3, NH2, NH(CH3), N(CH3)2, NH(C2H5) and N(C2H5)2.
-
-
-
-
搜索结果
5 条记录 (耗时 0.016 秒)
